2009 International Conference on Reconfigurable Computing and FPGAs最新文献_第5页

Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager SANI (Self-Adaptive Network Interface): NoC配置管理器的本地组件

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.62

Rachid Dafali, J. Diguet

引用次数: 6

Virtualization of Computing Resources in RCS for Multi-task Stream Applications 面向多任务流应用的RCS计算资源虚拟化

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.51

L. Kirischian, V. Dumitriu, P. Chun

{"title":"Virtualization of Computing Resources in RCS for Multi-task Stream Applications","authors":"L. Kirischian, V. Dumitriu, P. Chun","doi":"10.1109/ReConFig.2009.51","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.51","url":null,"abstract":"The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based Reconfigurable Computing Systems (RCS). In the presented “proof-of-concept” research the following topics have been investigated, developed and tested: i) architecture of a platform to support the dynamic allocation of Application Specific Virtual Processors (ASVP), ii) mechanisms for run-time on-chip assembly of ASVP from Virtual Hardware Components (VHC) and iii) mechanisms for run-time on-chip components (VHC) relocation in predetermined regions of the FPGA device. The above mechanisms have been implemented and tested on a specially developed platform: the Multi-task Adaptive Reconfigurable System (MARS) Platform. The actual application of MARS was prototyping a high-performance multi-mode stereo-vision system (200 fps) for the next generation of space-borne computing platforms.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131421084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High-Level FPGA Programming through Mapping Process Networks to FPGA Resources 通过映射过程网络到FPGA资源的高级FPGA编程

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.73

F. Mayer-Lindenberg

{"title":"High-Level FPGA Programming through Mapping Process Networks to FPGA Resources","authors":"F. Mayer-Lindenberg","doi":"10.1109/ReConFig.2009.73","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.73","url":null,"abstract":"We describe a simple and fast approach to FPGA programming that allows to efficiently exploit the numeric processing capabilities of recent FPGA chips. It basically consists in programming on top of a library of complex components for FPGA based scalable processor networks and providing a high-level programming interface to it. The FPGA application is presented as a network of processes which is automatically transformed into a corresponding network of simple processor components by a compiler. The compiler then generates individual program code for each of the simple processors. The coarse-grained processor network is eventually compiled into an FPGA configuration bitstream using standard FPGA tools at close-to-interactive speeds. Our approach has the additional benefit of being fully compatible with processor programming and extendible to mixed multi-component FPGA and processor systems. An experimental implementation of the process mapping scheme uses the p-Nets language that provides convenient structures for the presentation of the application processes and supports composite targets including processors linked to the FPGA chips. The evaluation of our concept on some FPGA chips includes an estimate of their floating point processing performances.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123521399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Lightweight Cryptography for FPGAs fpga的轻量级加密

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.54

P. Yalla, J. Kaps

引用次数: 123

Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation 基于fpga的异步逻辑故障注入仿真研究

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.35

M. Jeitler, J. Lechner

引用次数: 4

Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals 通过自定义指令和外设定制SHA-256和HMAC的可重构平台

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.40

M. Juliato, C. Gebotys

引用次数: 10

Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA FPGA上异步时钟运行时可重构模块网格的设计与性能

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.24

Jochen Strunk, Toni Volkmer, W. Rehm, H. Schick

{"title":"Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA","authors":"Jochen Strunk, Toni Volkmer, W. Rehm, H. Schick","doi":"10.1109/ReConFig.2009.24","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.24","url":null,"abstract":"This paper examines the feasibility of utilizing a grid of asynchronously clocked run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA. In contrast to a synchronously clocked grid studied in research, the design, the implementation, the performance and the resource utilization of an asynchronously clocked grid is shown. Such a run-time reconfigurable (RTR) grid on a FPGA can be utilized to dynamically offload compute functions on a host coupled system, providing multi-user and multi-context execution on behalf of user demands. For embedded systems it can be utilized as a highly dynamical platform by providing functional enhancement by module replacement during run-time. The presented platform leverages synthesis and development constraints and is able to increase the overall throughput by allowing multiple clock domains within the grid. The performance and the additional resource utilization of handling multiple clock domains is compared to synchronously clocked grids. As proof of concept a case study with a grid of 47 RTRMs is conducted on state of the art Virtex-5 FPGAs.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128215228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips 片上网络中阻塞时间对功耗影响的建模与分析

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.48

Arghavan Asad, A. E. Zonouz, M. Seyrafi, M. Soryani, M. Fathy

引用次数: 4

On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion 周期节律运动中心模式发生器的实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.81

C. Torres-Huitzil

引用次数: 5

A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks 一种基于收缩阵列的多变量多项式插值算法

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.70

R. Arce-Nazario, E. Orozco, D. Bollman

引用次数: 1