{"title":"面向多任务流应用的RCS计算资源虚拟化","authors":"L. Kirischian, V. Dumitriu, P. Chun","doi":"10.1109/ReConFig.2009.51","DOIUrl":null,"url":null,"abstract":"The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based Reconfigurable Computing Systems (RCS). In the presented “proof-of-concept” research the following topics have been investigated, developed and tested: i) architecture of a platform to support the dynamic allocation of Application Specific Virtual Processors (ASVP), ii) mechanisms for run-time on-chip assembly of ASVP from Virtual Hardware Components (VHC) and iii) mechanisms for run-time on-chip components (VHC) relocation in predetermined regions of the FPGA device. The above mechanisms have been implemented and tested on a specially developed platform: the Multi-task Adaptive Reconfigurable System (MARS) Platform. The actual application of MARS was prototyping a high-performance multi-mode stereo-vision system (200 fps) for the next generation of space-borne computing platforms.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Virtualization of Computing Resources in RCS for Multi-task Stream Applications\",\"authors\":\"L. Kirischian, V. Dumitriu, P. Chun\",\"doi\":\"10.1109/ReConFig.2009.51\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based Reconfigurable Computing Systems (RCS). In the presented “proof-of-concept” research the following topics have been investigated, developed and tested: i) architecture of a platform to support the dynamic allocation of Application Specific Virtual Processors (ASVP), ii) mechanisms for run-time on-chip assembly of ASVP from Virtual Hardware Components (VHC) and iii) mechanisms for run-time on-chip components (VHC) relocation in predetermined regions of the FPGA device. The above mechanisms have been implemented and tested on a specially developed platform: the Multi-task Adaptive Reconfigurable System (MARS) Platform. The actual application of MARS was prototyping a high-performance multi-mode stereo-vision system (200 fps) for the next generation of space-borne computing platforms.\",\"PeriodicalId\":325631,\"journal\":{\"name\":\"2009 International Conference on Reconfigurable Computing and FPGAs\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 International Conference on Reconfigurable Computing and FPGAs\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ReConFig.2009.51\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Reconfigurable Computing and FPGAs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2009.51","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Virtualization of Computing Resources in RCS for Multi-task Stream Applications
The possibility for distribution of FPGA resources in the temporal domain for multi-modal & multi-task workloads conceptually allows virtualization of logic, communication and input/output resources similar to memory virtualization in advanced conventional computers (e.g. superscalar). This, in turn, can dramatically increase the cost-effectiveness of FPGA based Reconfigurable Computing Systems (RCS). In the presented “proof-of-concept” research the following topics have been investigated, developed and tested: i) architecture of a platform to support the dynamic allocation of Application Specific Virtual Processors (ASVP), ii) mechanisms for run-time on-chip assembly of ASVP from Virtual Hardware Components (VHC) and iii) mechanisms for run-time on-chip components (VHC) relocation in predetermined regions of the FPGA device. The above mechanisms have been implemented and tested on a specially developed platform: the Multi-task Adaptive Reconfigurable System (MARS) Platform. The actual application of MARS was prototyping a high-performance multi-mode stereo-vision system (200 fps) for the next generation of space-borne computing platforms.