{"title":"Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager","authors":"Rachid Dafali, J. Diguet","doi":"10.1109/ReConFig.2009.62","DOIUrl":null,"url":null,"abstract":"This paper presents our approach considering the needs of reconfiguration in the domain of NoCs. We introduce our motivations and then detail our strategy based on local (delegate) and global configuration managers. Finally we describe an original self-adaptive Network Interface architecture, which is a part of the configuration manager, in charge of run-time buffer sizing. The challenge is clearly a tradeoff between the complexity of decision implementation and expected gains in terms of cost and performances. Our results obtained on FPGA within an emulator board demonstrate the interest of the proposed approach.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Reconfigurable Computing and FPGAs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2009.62","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
This paper presents our approach considering the needs of reconfiguration in the domain of NoCs. We introduce our motivations and then detail our strategy based on local (delegate) and global configuration managers. Finally we describe an original self-adaptive Network Interface architecture, which is a part of the configuration manager, in charge of run-time buffer sizing. The challenge is clearly a tradeoff between the complexity of decision implementation and expected gains in terms of cost and performances. Our results obtained on FPGA within an emulator board demonstrate the interest of the proposed approach.