2009 International Conference on Reconfigurable Computing and FPGAs最新文献_第4页

An Optimized System for Multiple Sequence Alignment 一个优化的多序列比对系统

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/RECONFIG.2009.82

M. Gok

引用次数: 4

Observing the Randomness in RO-Based TRNG 观察基于ro的TRNG中的随机性

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.57

Nathalie Bochard, F. Bernard, V. Fischer

{"title":"Observing the Randomness in RO-Based TRNG","authors":"Nathalie Bochard, F. Bernard, V. Fischer","doi":"10.1109/ReConFig.2009.57","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.57","url":null,"abstract":"The paper deals with true random number generators using a set of ring oscillators as proposed by Sunar et al. in 2007. The original generator has been recently enhanced by Wold and Tan by introducing flip-flops at the output of each ring. We show in the first part of the paper that both original and enhanced architectures have exactly the same behavior when composed of ideal components (they have the same mathematical model), but they have very different behavior in physical devices, as observed by Wold and Tan. However, while reducing the number of rings as they have proposed, the security proof of Sunar et al. does not hold any more. In order to demonstrate that, we will show that the proportion of the pseudo-randomness compared to the true-randomness in the generated random raw signal is much bigger than expected. Our simulation model shows that the generator using more than 18 ideal jitter-free rings having slightly different frequencies and producing thus only pseudo-randomness, will always let the tests pass. We conclude that reducing the number of rings not only makes the security proof of Sunar et al. not hold, but it makes the generator more vulnerable, since the pseudo-randomness is easy to manipulate.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 36

Low Power RTL Exploration Mechanism Based on the Cache Parameters 基于缓存参数的低功耗RTL探测机制

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.63

A. Silva-Filho, Sidney M. L. Lima, F. C. Cox

引用次数: 0

MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs 基于MRAM的eFPGAs:编程和硅流，勘探环境，MRAM在工业中的现状及其在fpga中的独特潜力

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.25

Yoann Guillemenet, S. Z. Ahmed, L. Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, G. Sassatelli

{"title":"MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs","authors":"Yoann Guillemenet, S. Z. Ahmed, L. Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, G. Sassatelli","doi":"10.1109/ReConFig.2009.25","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.25","url":null,"abstract":"The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (Magnetoresistive Random Access Memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which are only possible with SRAM based FPGAs. MRAMs have potential to bridge this gap. This paper will present a brief survey of our work in this regard for creating the entire eco system of software and hardware tool flows, MRAM layout work at 120nm, exploration environments to conduct complex experiments especially Dynamic Reconfiguration and Multi Context FPGAs. MRAM opens new opportunities for them compared to SRAM and Flash. It will discuss the current status of MRAM in industry and our current and future test chips road maps. Provide several references to industry and our published work for details about MRAMs and eFPGAs, to show why we think MRAM can be very interesting element for FPGAs.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132241304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip 基于片上硬连线网络的fpga可组合和持久状态应用交换

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.64

Muhammad Aqeel Wahlah, K. Goossens

引用次数: 2

Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms 在可重构处理器中实现保护区域以隔离执行加密算法

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.46

Ahmet Onur Durahim, E. Savaş, Kazim Yumbul

{"title":"Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms","authors":"Ahmet Onur Durahim, E. Savaş, Kazim Yumbul","doi":"10.1109/ReConFig.2009.46","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.46","url":null,"abstract":"We design and realize a protected zone inside a reconfigurable and extensible embedded RISC processor for isolated execution of cryptographic algorithms. The protected zone is a collection of processor subsystems such as functional units optimized for high-speed execution of integer operations, a small amount of local memory, and general- and special-purpose registers. We outline the principles for secure software implementation of cryptographic algorithms in a processor equipped with the protected zone. We also demonstrate the efficiency and effectiveness of the protected zone by implementing major cryptographic algorithms, namely RSA, elliptic curve cryptography, and AES in the protected zone. In terms of time efficiency, software implementations of these three cryptographic algorithms outperform equivalent software implementations on similar processors reported in the literature. The protected zone is designed in such a modular fashion that it can easily be integrated into any RISC processor; its area overhead is considerably moderate in the sense that it can be used in vast majority of embedded processors. The protected zone can also provide the necessary support to implement TPM functionality within the boundary of a processor.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A 10 Gbps OTN Framer Implementation Targeting FPGA Devices 针对FPGA器件的10gbps OTN帧实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/RECONFIG.2009.27

G. Guindani, Frederico Ferlini, J. Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, F. Moraes

引用次数: 8

Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers 有效的PGA LFSR白伪随机数实现

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.11

L. Colavito, D. Silage

引用次数: 16

Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures 粗粒度动态可重构体系结构热点发展的预防

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.18

Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, T. Kuhn, W. Rosenstiel

引用次数: 2

Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications 面向DSP应用的粗粒度动态可重构架构设计

2009 International Conference on Reconfigurable Computing and FPGAs Pub Date : 2009-12-09 DOI: 10.1109/ReConFig.2009.49

Chenxin Zhang, T. Lenart, Henrik Svensson, V. Öwall

引用次数: 18