{"title":"Low Power RTL Exploration Mechanism Based on the Cache Parameters","authors":"A. Silva-Filho, Sidney M. L. Lima, F. C. Cox","doi":"10.1109/ReConFig.2009.63","DOIUrl":null,"url":null,"abstract":"Cache memory is a usual architecture component, and has the function of increasing the system’s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 International Conference on Reconfigurable Computing and FPGAs","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ReConFig.2009.63","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Cache memory is a usual architecture component, and has the function of increasing the system’s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases.