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2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)最新文献

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A 250Mbps 100kV/µs CMTI On-Chip Double-Isolated Transformer-Based Digital Isolator 250Mbps 100kV/µs基于CMTI片上双隔离变压器的数字隔离器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963044
Zhiyong Xiong, Dongfang Pan, Guolong Li, Lin Cheng
{"title":"A 250Mbps 100kV/µs CMTI On-Chip Double-Isolated Transformer-Based Digital Isolator","authors":"Zhiyong Xiong, Dongfang Pan, Guolong Li, Lin Cheng","doi":"10.1109/ICTA56932.2022.9963044","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963044","url":null,"abstract":"This paper presents a double-isolated on-chip transformer-based digital isolator exploiting integrated double SiO2 galvanic barriers to achieve an isolation rate of 4kV. The isolator employs pulse polarity modulation to reduce the power consumption while maintaining a high data rate and high common mode transient immunity (CMTI). Simulation results show that the proposed isolator achieves a 250Mbps maximum data rate with a 5ns propagation delay and a 100kV/µs CMTI performance. With a load of 15pF, TX and RX consume 0.32mA and 3.4mA currents at a 1Mbps data rate and 11.7mA and 3.5mA currents at a 250Mbps data rate, respectively.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134226064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 30W and 95% Efficiency Class-E Wireless Power Transfer Transmitter with Vector Algorithm Control 一个30W和95%效率的e类无线电力传输发射机与矢量算法控制
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9962971
Shangzhou Zhao, Zhongming Xue, Yuhao Xiong, Zhuoneng Li, Xihao Liu, Yongchao Zhang, Zhuoqi Guo, Li Geng
{"title":"A 30W and 95% Efficiency Class-E Wireless Power Transfer Transmitter with Vector Algorithm Control","authors":"Shangzhou Zhao, Zhongming Xue, Yuhao Xiong, Zhuoneng Li, Xihao Liu, Yongchao Zhang, Zhuoqi Guo, Li Geng","doi":"10.1109/ICTA56932.2022.9962971","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962971","url":null,"abstract":"This paper proposes a vector algorithm control (VAC) method for class-E power amplifier (PA) to compensate the variation of load resistance based on an introduced mathematical model. In contrast to the conventional Class-E PA adaptive control method with impedance matching, which introduces additional power loss, the proposed VAC loop directly adjusts the core parameters of the Class-E PA, thus enhances the system efficiency. A transmitter applicable to wireless power transfer (WPT) systems is implemented to verify the proposed VAC loop. Simulation results show that the system achieves a peak output power of 30W and a very high peak efficiency of 95% with wide variable loads.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134556812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS 一种用于40纳米CMOS共封装光学器件的0.58 pj /bit 56-Gb/s PAM-4光接收机前端和包络跟踪器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963048
Yue Yu, Da Ming, Min Tan
{"title":"A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS","authors":"Yue Yu, Da Ming, Min Tan","doi":"10.1109/ICTA56932.2022.9963048","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963048","url":null,"abstract":"A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114308749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CGP-based Efficient Approximate Multiplier with Error Compensation 基于cpp的误差补偿高效近似乘法器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963083
Qi Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao
{"title":"A CGP-based Efficient Approximate Multiplier with Error Compensation","authors":"Qi Shen, Renyuan Zhang, Hao Zhang, Hao Cai, Bo Liu, Jian Xiao","doi":"10.1109/ICTA56932.2022.9963083","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963083","url":null,"abstract":"As one of the most promising energy-efficient paradigms in deploying Neural Network (NN) on hardware, approximate computing ($A$ xC) has recently gained great traction to replace exact computing. This paper proposes an efficient approximate multiplier design method, which combines the Cartesian Genetic Programming (CGP)-based automatic design method and manual design method. Besides, an error compensation scheme based on the traversal search of truth table is proposed for higher-order multiplier construction. Experiments show that compared to exact multiplier, the proposed approximate multiplier can reduce the area, power consumption, and delay by 54.9%, 55.7%, and 36.86%, respectively. It also shows superiority to the state-of-the-art approximate multiplier. In addition, when deployed in LeNet-5 for MINIST datasets, the proposed multipliers show higher efficiency than exact multiplier with comparable recognition accuracy.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116156518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Wideband and High Output Swing Analog Frontend Circuit for FMCW LiDAR 一种用于FMCW激光雷达的宽带高输出摆幅模拟前端电路
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963043
Yivun Xie, Youze Xin, Bing Zhang, Ruipeng Yang, Yaoxin Li, Li Geng
{"title":"A Wideband and High Output Swing Analog Frontend Circuit for FMCW LiDAR","authors":"Yivun Xie, Youze Xin, Bing Zhang, Ruipeng Yang, Yaoxin Li, Li Geng","doi":"10.1109/ICTA56932.2022.9963043","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963043","url":null,"abstract":"This paper proposes a low input impedance, high output swing column-level analog front-end (AFE) circuit for the frequency modulation continuous wave (FMCW) LiDAR. The AFE circuit adopts a shunt-feedback transimpedance amplifier (TIA) and an output swing compensation limiting amplifier (LA) to amplify the weak echo signal and realize the high output swing. The input direct current cancellation (IDCC) circuit is used to stabilize the output direct operating point, where the lag network is used to extend the frequency range of high gain, and the noise of the direct current is reduced by means of noise transfer. The proposed AFE circuit is implemented in a 55nm CMOS process, and the post-layout simulation results show that the circuit achieves a gain of more than 118.7 dBΩand an output swing of higher than 840 mV in the frequency range of 26 MHz∼400 MHz. The input-referred noise current is 12.45 pA/Hz0.5 and the power consumption is 7 mW with a 1.2 V power supply.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122504789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High Reliability Sensing Amplifier for Hybrid MTJ/CMOS Circuits 一种用于混合MTJ/CMOS电路的高可靠性传感放大器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963012
Jiawei Fu, Pengcheng Wu, Hao Cai
{"title":"A High Reliability Sensing Amplifier for Hybrid MTJ/CMOS Circuits","authors":"Jiawei Fu, Pengcheng Wu, Hao Cai","doi":"10.1109/ICTA56932.2022.9963012","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963012","url":null,"abstract":"Spin transfer torque magnetic tunnel junction (STT-MTJ) based MRAM shows great performance such as zero standby power, outstanding CMOS compatibility, high density and endurance. Hybrid MTJ/CMOS circuits have been extensively studied for energy efficient applications. However, MRAM sensing operations still suffer from reliability issue owing to the inevitable process variations, voltage and temperature fluctuations. This paper proposes a high reliability sensing amplifier (HRSA) for hybrid MTJ/CMOS circuits, simulation is performed based on 28-nm CMOS design kit and 40-nm MTJ model. Simulation results show that the proposed sensing circuit achieves a lower sensing error rate (SER) compared to previous works over a wide temperature range (-55°C∽125°C). Proposed HRSA exhibits excellent tolerance to the temperature and process variations.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127216609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Floorplanning and Power/Ground Network Design for A Programmable Vision Chip 一种可编程视觉芯片的平面规划和电源/接地网络设计
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963051
Haozhe Xu, Siyuan Wei, Nan Qi, Peng Wu, Jian Liu, N. Wu, Liyuan Liu, Shuangming Yu
{"title":"Floorplanning and Power/Ground Network Design for A Programmable Vision Chip","authors":"Haozhe Xu, Siyuan Wei, Nan Qi, Peng Wu, Jian Liu, N. Wu, Liyuan Liu, Shuangming Yu","doi":"10.1109/ICTA56932.2022.9963051","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963051","url":null,"abstract":"A programmable vision chip integrates a high-speed image sensor and a vision processor on one single chip. It can be adapted to both traditional CV (computer vision) algorithms and deep learning algorithms efficiently. The chip is compute-intensive and memory-intensive, physical design of the chip encounters challenges. This article will introduce a floorplanning and power planning approach appropriate for this large-scale vision chip, limit the influence of IR drop, and finally compare the performance of this experimental result with state-of-the-art chips.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133519734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two-bit multi-level spin orbit torque MRAM with the fully one-step write operation 具有完全一步写入操作的2位多级自旋轨道扭矩MRAM
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9963089
Chenyi Wang, Min Wang, Zhaohao Wang, Weisheng Zhao
{"title":"Two-bit multi-level spin orbit torque MRAM with the fully one-step write operation","authors":"Chenyi Wang, Min Wang, Zhaohao Wang, Weisheng Zhao","doi":"10.1109/ICTA56932.2022.9963089","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9963089","url":null,"abstract":"As an emerging non-volatile memory technology, the spin orbit torque magnetic random access memory (SOT-MRAM) has attracted intensive research interest due to its advanced performance. However, the binary storage feature of the SOT-MRAM has become one of the obstacles. In this paper, we present a study of two-bit multi-level SOT-MRAM where two canted in-plane-anisotropy magnetic tunnel junctions (MTJs) store a pair of data. Compared with the previous schemes of multi-level SOT-MRAMs, our proposal enables fully one-step writing without the need of the preset operation. Micromagnetic simulation is performed to validate the functionality of the proposed multi-level cell (MLC) SOT-MRAM, meanwhile, the details of magnetization switching are clearly shown. Simulation results also demonstrate that the device could accomplish the magnetization switching at the sub-nanosecond speed and continuously decreasing power consumption with the size scaling down. In addition, the dipolar field between two cells has little influence on the switching process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133264022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 14.39ppm/kPa Stress Sensor with Low Temperature-drift and High Linearity for turbulence Stress 一种具有低温度漂移和高线性湍流应力的14.39ppm/kPa应力传感器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9962985
Lanxiang Xiao, Lei Chen, F. An
{"title":"A 14.39ppm/kPa Stress Sensor with Low Temperature-drift and High Linearity for turbulence Stress","authors":"Lanxiang Xiao, Lei Chen, F. An","doi":"10.1109/ICTA56932.2022.9962985","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962985","url":null,"abstract":"In the analysis and calculation of turbulent flow, the stress generated by the fluid needs to be accurately measured by sensors. In this research, a mechanical stress sensor was developed based on standard 180nm CMOS technology for real-time measurement of stress. The main contributions of this study include the following: 1) The temperature-compensated RC oscillator circuit changes mechanical stress-induced chip deformation into a frequency output. When the temperature was changed from -40°C to 120°C, the oscillator frequency only changed to 0.303Hz/ °C. 2) No complicated calibration and complicated measurement equipment are required. The chip area does not exceed 0.569 mm2. Moreover, the power consumption does not exceed 22.9 µW. 3) The average sensitivity measured by the chip is 14.39ppm/kPa, and the linear fitting curve's determination coefficient (R2) is 0.9983.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122977377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC 一种用于高速流水线ADC的85dB SFDR输入缓冲器
2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA) Pub Date : 2022-10-28 DOI: 10.1109/ICTA56932.2022.9962993
Cece Huang, Yuanfu Zhao, Yafei Ji, Xin Yang, Tieliang Zhang, Weixin Gai
{"title":"An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC","authors":"Cece Huang, Yuanfu Zhao, Yafei Ji, Xin Yang, Tieliang Zhang, Weixin Gai","doi":"10.1109/ICTA56932.2022.9962993","DOIUrl":"https://doi.org/10.1109/ICTA56932.2022.9962993","url":null,"abstract":"This paper presents a high linearity input buffer with proposed two-level bootstrapping scheme for high-speed pipeline ADC. In high input frequency, the parasitic capacitance of active devices and inductance of packaging are the main sources of non-linearity. In order to improve the linearity, the proposed input buffer drives the bootstrapping block by the output signal instead of the input, which prevents the non-linear sink current from flowing through the inductance, and thus the linearity is improved. The input buffer was designed together with a 14-bit 500MSPS pipeline ADC in a 28nm CMOS technology. The measured results show that the SFDR achieves 85dB at 2ndNyquist frequency, which is 8dB larger than the conventional one.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124231259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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