一种用于40纳米CMOS共封装光学器件的0.58 pj /bit 56-Gb/s PAM-4光接收机前端和包络跟踪器

Yue Yu, Da Ming, Min Tan
{"title":"一种用于40纳米CMOS共封装光学器件的0.58 pj /bit 56-Gb/s PAM-4光接收机前端和包络跟踪器","authors":"Yue Yu, Da Ming, Min Tan","doi":"10.1109/ICTA56932.2022.9963048","DOIUrl":null,"url":null,"abstract":"A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS\",\"authors\":\"Yue Yu, Da Ming, Min Tan\",\"doi\":\"10.1109/ICTA56932.2022.9963048\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963048\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

提出了一种具有包络跟踪器的40nm CMOS共封装光学器件(CPO)的56Gb/s PAM-4光接收机前端。对基于逆变器的并联反馈跨阻放大器(TIA)进行了低噪声、高线性度的优化设计,并采用连续时间线性均衡器(CTLE)实现高频升压。采用db线性变增益放大器(VGA)实现分贝线性增益控制。包络跟踪器用于提取接收信号的包络,为自动增益控制回路提供控制电压。布局后仿真表明,本文在40 nm CMOS工艺下实现了0.58pJ/bit的56Gb/s PAM-4光接收机前端。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS
A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信