{"title":"一种用于40纳米CMOS共封装光学器件的0.58 pj /bit 56-Gb/s PAM-4光接收机前端和包络跟踪器","authors":"Yue Yu, Da Ming, Min Tan","doi":"10.1109/ICTA56932.2022.9963048","DOIUrl":null,"url":null,"abstract":"A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS\",\"authors\":\"Yue Yu, Da Ming, Min Tan\",\"doi\":\"10.1109/ICTA56932.2022.9963048\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963048\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963048","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.58-pJ/bit 56-Gb/s PAM-4 Optical Receiver Frontend with an Envelope Tracker for Co-Packaged Optics in 40-nm CMOS
A 56Gb/s PAM-4 optical receiver frontend with a envelope tracker for co-packaged optics (CPO) in 40-nm CMOS technology is presented. An inverter-based shunt-feedback transimpedance amplifier (TIA) is carefully optimized for low noise and high linearity, and a continuous time linear equalizer (CTLE) is adopted for high frequency boosting. A dB-linear variable gain amplifier (VGA) is adopted to realize decibel-linear gain control. An envelope tracker is used to extract the envelope of the received signal, which provides the control voltage for the automatic gain control loop. Post-layout simulations show that this work achieves a 56Gb/s PAM-4 optical receiver frontend with 0.58pJ/bit in 40-nm CMOS process.