An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC

Abstract

This paper presents a high linearity input buffer with proposed two-level bootstrapping scheme for high-speed pipeline ADC. In high input frequency, the parasitic capacitance of active devices and inductance of packaging are the main sources of non-linearity. In order to improve the linearity, the proposed input buffer drives the bootstrapping block by the output signal instead of the input, which prevents the non-linear sink current from flowing through the inductance, and thus the linearity is improved. The input buffer was designed together with a 14-bit 500MSPS pipeline ADC in a 28nm CMOS technology. The measured results show that the SFDR achieves 85dB at 2ndNyquist frequency, which is 8dB larger than the conventional one.