2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)最新文献_第8页

A radiation-tolerant ring oscillator phase-locked loop in 0.13µm CMOS 一种0.13µm CMOS耐辐射环形振荡器锁相环

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6291945

Lei Chen, X. Wen, Y. You, D. Huang, Changzhi Li, Jinghong Chen

{"title":"A radiation-tolerant ring oscillator phase-locked loop in 0.13µm CMOS","authors":"Lei Chen, X. Wen, Y. You, D. Huang, Changzhi Li, Jinghong Chen","doi":"10.1109/MWSCAS.2012.6291945","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291945","url":null,"abstract":"Advanced CMOS technologies have demonstrated reduced sensitivity to radiation total-ionization-dose (TID) effect. However, the reduced device dimensions can significantly increase the circuit sensitivity to transient radiation effects. This paper presents a radiation-tolerant ring oscillator Phase-Locked Loop (PLL) designed in a commercial 0.13 μm CMOS process. The PLL is designed for radiation-tolerant high-speed serial link applications. It operates over a frequency range of 1.1 GHz to 4.4 GHz with an RMS jitter of 1.8 ps at 3.125 GHz. The phase frequency detector (PFD) and frequency divider (FD) are designed with a novel D-flip-flop (DFF) that is robust to single event radiation effects (SEEs). The voltage-controlled oscillator (VCO) is designed with two ring oscillators cross-coupled thus compensating each other with the radiation-induced transient currents. Each ring oscillator has its own control voltage driven by an independent charge pump and loop filter. The redundancy helps to mitigate radiation strikes on the VCO control voltage. Simulation results show that the proposed PLL demonstrates radiation immunity for critical charge values up to 250 fC and can recover quickly from radiation strikes on its sensitive nodes. The PLL operates under a 1.2 V power supply and consumes 40 mW of power.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124490015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Charge-pump based switched-capacitor gain stage 基于电荷泵的开关电容增益级

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292018

Alireza Nilchi, D. Johns

引用次数: 1

Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control 超io - gb /s CMOS CML延迟控制缓冲电路的设计方法

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292092

K. Kishine, H. Inaba, Y. Ohtomo, M. Nakamura, Mitsuo Nakamura

引用次数: 1

Blocker and jitter tolerant wideband ΣΔ modulators 阻断和抗抖动宽带ΣΔ调制器

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292039

J. Silva-Martínez, A. Karsilayan, Hemasundar Mohan Geddada

引用次数: 2

Validation of a reflected-impedance design method for wireless power transfer applications 无线电力传输应用中反射阻抗设计方法的验证

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292131

D. Beams, S. G. Annam

引用次数: 7

Using constraint graphs to improve embedded systems design 利用约束图改进嵌入式系统设计

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292090

Indira Jayaram, C. Purdy

引用次数: 2

Rank modulation hardware for flash memories 用于闪存的等级调制硬件

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292015

Mina Kim, J. Park, C. Twigg

引用次数: 14

Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs 基于sram的Altera fpga的低面积开销ARQ软容错数据路径研究

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292047

Phani Balaji Swamy Tangellapalli, S. R. Hasan

{"title":"Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs","authors":"Phani Balaji Swamy Tangellapalli, S. R. Hasan","doi":"10.1109/MWSCAS.2012.6292047","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292047","url":null,"abstract":"The SRAM-based FPGA, due to their high performance, has become a popular choice in today's electronic systems and are used in large number of applications. But in radiation harsh environment these FPGAs require some additional mechanism to cope up with soft errors. Modern FPGAs are built in 28nm technologies, where even combinational circuits are substantially vulnerable to soft errors. Such designs require soft error mitigation circuits in their data paths. Conventional soft error mitigation techniques such as triple modular redundancy are robust but their area overhead is three times as compared to normal design. In this paper a variant of automatic repeat request (ARQ) protocol is proposed, along with delayed redundancy to reduce area overhead. Synthesis results show an improvement of 9.1 and 10% in latency for Cyclone II and Stratix II FPGAs, respectively, with a 1.94 times improvement in resource utilization. Our synthesis results show that our implementation is not only better in terms of area overhead but if a soft error occurs once in 10 clock cycles the overall system throughput is better for the proposed architecture compared to TMR. To our knowledge this is the first work to implement ARQ based protocol utilizing delayed redundancy to mitigate soft errors in SRAM-based FPGAs.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129410592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the invariance of Lazzaro circuit model 论Lazzaro电路模型的不变性

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6292238

C. Marinov, R. Costea, V. Bucata

引用次数: 1

A 30–40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology 使用Verilog-A高级设计方法开发30-40 GHz分数n频率合成器

2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2012-09-05 DOI: 10.1109/MWSCAS.2012.6291956

G. Gal, Omar Abdelfattah, G. Roberts

{"title":"A 30–40 GHz fractional-N frequency synthesizer development using a Verilog-A high-level design methodology","authors":"G. Gal, Omar Abdelfattah, G. Roberts","doi":"10.1109/MWSCAS.2012.6291956","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291956","url":null,"abstract":"A design methodology for constructing a high-frequency (30 to 40 GHz) fractional-N synthesizer in a 65 nm TSMC CMOS process is presented. The method is focused on minimizing the phase noise at the output of the synthesizer while achieving the desired frequency range and frequency resolution. The method involves selecting initial values for each PLL component, simulating each using a transistor-level simulation, i.e. Spectre, and deriving a noise and linearity model of operation. Using an initial guess for the loop filter transfer function, together with a set of Verilog-A models for the various PLL components, the loop filter transfer function is adjusted so that the output phase noise behaviour is minimized. If the noise performance does not meet specifications, noise and linearity bounds on the individual PLL components can be derived. These, in turn, will force the re-design of all or some of the PLL components. The approach described here has been used to design a fractional-N synthesizer in the frequency range of 30 - 40 GHz with 5 MHz frequency steps having a phase noise of less than -90 dBc/Hz at a 1000 kHz frequency offset.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127065590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5