{"title":"Thermal sensor design for 3D ICs","authors":"F. Kashfi, J. Draper","doi":"10.1109/MWSCAS.2012.6292062","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292062","url":null,"abstract":"Thermal measurement and management is crucial in three dimensional integrated circuits (3DICs) technology because increasing temperature stress is one of the main challenges due to high power density. Because of the physical adjacency and use of Through Silicon Vias (TSVs) as thermal exchangers between the stacked layers, the thermal profiles of the layers are highly correlated with each other. Any planar hotspot in a layer in a 3DIC is converted to a volumetric spatial hotspot. Run time thermal management in 3DICs requires proper monitoring and measurement of these spatial hotspots inside the chip. Having spatial hotspots and high thermal correlation between layers is a motivation for designing 3D thermal sensors. A new ring oscillator based 3D thermal sensor is proposed in this paper. Use of this sensor will reduce total number of needed sensors to monitor a typical whole 3DIC by 48% with same reading error in comparison with use of conventional 2D sensors.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124042469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Angelina Espejel Trujillo, Ivan Castillo-Camacho, M. Nakano-Miyatake, Gina Gallegos-García, H. Meana
{"title":"Improved secret image sharing scheme with payload optimization","authors":"Angelina Espejel Trujillo, Ivan Castillo-Camacho, M. Nakano-Miyatake, Gina Gallegos-García, H. Meana","doi":"10.1109/MWSCAS.2012.6292224","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292224","url":null,"abstract":"This paper presents an improvement of interpolation-based (k,n)-threshold secret image sharing (SIS) scheme, where a secret data payload is optimized using Lagrange Interpolation operated in GF(28). A secret data can be not only images but also any type of files, such as documents and executable files, which is hidden using Least Significant Bit (LSB) steganography into n innocent-looking images called camouflage images. In order to recover the secret data, at least k (≤n) camouflage images are required. The proposed scheme provides an authentication mechanism by parity-bit checking and lossless recovery of the secret data using GF(28) operation. Controlling the value of k, the size of camouflage images can be controlled to avoid a pixel expansion occurred in conventional SIS schemes.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"9 18","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120808294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A neuromorphic circuit that computes differential motion","authors":"Ko-Chung Tseng, A. C. Parker","doi":"10.1109/MWSCAS.2012.6291964","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291964","url":null,"abstract":"Detecting moving objects in a moving background or a dynamic scene is essential to the survival of some animals. The circuitry computing differential motion is found in the biological retina. An object-motion-sensitivity (OMS) ganglion cell remains silent under global motion of the entire image but fires when the image patch in its receptive field moves differently from the background. In this paper, we present a neuromorphic circuit that compares the motion speeds of the central receptive field and peripheral receptive field. We demonstrate that there is a response if motion speeds of the central and peripheral receptive fields are different. However, the response is suppressed if motion speeds of central and peripheral receptive fields are the same.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132334065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Compact low-voltage CMOS analog divider using a four-quadrant multiplier and biasing control circuit","authors":"I. Padilla-Cantoya","doi":"10.1109/MWSCAS.2012.6292067","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292067","url":null,"abstract":"A compact low-voltage analog divider is presented. The design is based on a four-quadrant multiplier and a differential transconductance amplifier as basic building blocks operating in voltage mode. A biasing control circuit to set the dc operational point that requires very few devices and offers continuous-time operation is included. Experimental results of a test chip in 0.5μm CMOS technology verify the proposed operation.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ulaganathan, B. Blalock, J. Holleman, C. Britton
{"title":"An ultra-low voltage self-startup charge pump for energy harvesting applications","authors":"C. Ulaganathan, B. Blalock, J. Holleman, C. Britton","doi":"10.1109/MWSCAS.2012.6291993","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291993","url":null,"abstract":"An ultra-low voltage, self-starting, switched-capacitor based charge pump is proposed for energy harvesting applications. The integrated linear charge pump topology presented in this work has been optimized for low-voltage start-up. The control signals for the charge-transfer switches (CTS), generated using two clock phases, reduce reverse currents and thus improve the efficiency of the converter. Adiabatic switching techniques have been employed to reduce the switching losses associated with the CTS gate control. This design has been implemented in a 130-nm CMOS process. Simulation results demonstrate a low startup voltage of 125 mV with efficiency of 62 % for a static current load of 0.1 μA.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130678381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Fu, V. Koomson, Pengfei Wu, Shengling Deng, Z. R. Huang
{"title":"Design of an integrated high-speed HBT-based electroabsorption modulator and driver in SiGe BiCMOS technology","authors":"E. Fu, V. Koomson, Pengfei Wu, Shengling Deng, Z. R. Huang","doi":"10.1109/MWSCAS.2012.6291951","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6291951","url":null,"abstract":"Monolithic optoelectronic integrated circuits are a primary focus of research for high-speed optical communication system development. Standard silicon processes provide a cost effective way for electro-optic system integration. This paper presents a monolithic optical modulator and driver design based on 130nm SiGe BiCMOS technology. Post-layout simulation results demonstrate that the modulator achieves a switch frequency of 10GHz.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132815490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Field programmable switched capacitor voltage converter","authors":"Chao Li, Jordi Cosp-Vilella, H. Martínez","doi":"10.1109/ICECS.2012.6463551","DOIUrl":"https://doi.org/10.1109/ICECS.2012.6463551","url":null,"abstract":"In this paper we show two different schemes to implement a field programmable circuit that can connect n capacitors as a charge-pump of, eventually, any topology and switching pattern. Capacitor connectivity is configured by means of registers that control multiplexers that, in turn, select the phase signal that controls each switch. It is also shown that, with any of these schemes, dynamic configuration of the circuit may be achieved by simply adding additional control phases.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132908440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of wideband continuous-time ΔΣ ADCs using two-step quantizers","authors":"S. Balagopal, V. Saxena","doi":"10.1109/MWSCAS.2012.6292038","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292038","url":null,"abstract":"Continuous-time delta sigma (CT-ΔΣ) ADCs are established as the data conversion architecture of choice for the next-generation wireless applications. Several efforts have been made to simultaneously improve the bandwidth and dynamic range of ΔΣ ADCs. We proposed using two-step quantizer in a single-loop CT-ΔΣ modulator to achieve higher conversion bandwidth. This paper presents a tutorial for employing the design technique through a 130n CMOS implementation. The proposed 640 MS/s, 4th order continuous-time delta sigma modulator (CT-ΔΣM) incorporates a two-step 5-bit quantizer, consisting of only 13 comparators. The CT-ΔΣM achieves a dynamic range of 70 dB, peak SNDR of 65.3 dB with 32 MHz bandwidth (OSR = 10) while consuming only 30 mW from the 1.2 V supply. The relevant design trade offs have been discussed and presented with simulation results.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128379654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reducing thermal hotspots in microprocessors with expanded component sizing","authors":"S. Eratne, E. John, Byeong Kil Lee","doi":"10.1109/MWSCAS.2012.6292100","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292100","url":null,"abstract":"Thermal hotspots are a destructive phenomenon occurring in contemporary microprocessors. High power density of microprocessors and excessive use of certain microprocessor components by applications are considered the primary causes of increased temperature. Dynamic Thermal Management Techniques used in mitigating excessive temperatures results in throttling of clock speed, which degrades the performance of the microprocessor. In this paper we propose a simple but novel technique to reduce hotspots in microprocessors. We propose to lower the power density of selected high temperature components by increasing the chip area of that component. We select thermally susceptible components that have small footprints and increase the area of such components, thereby reducing the occurrence of hotspots. The overall chip area increase is minimal and our research has shown that the associated delay penalty is negligible.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134222526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A digitally assisted, pseudo-resistor-less amplifier in 65nm CMOS for neural recording applications","authors":"Yi Chen, A. Basu, M. Je","doi":"10.1109/MWSCAS.2012.6292033","DOIUrl":"https://doi.org/10.1109/MWSCAS.2012.6292033","url":null,"abstract":"A novel scheme for amplification in neural recording systems is proposed in this work that allows us to remove the large `pseudo-resistors' needed to bias the typically used capacitive amplifier topology. Comparison and reset circuits are implemented with the core amplifier to fold the output waveform of amplifier into a preset range for digitizing by an ADC. A reconstruction algorithm is then used in the digital domain to recover the amplified signal from the folded waveform. By removing the pseudo-resistors, higher robustness, less noise in LFP band and better matching and programmability of high pass corner can be achieved in the proposed design. Simulation and measurement results are presented from a prototype fabricated in 65nm CMOS. The presented scheme is general and can be used with any capacitive amplifier.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132933541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}