基于sram的Altera fpga的低面积开销ARQ软容错数据路径研究

Phani Balaji Swamy Tangellapalli, S. R. Hasan
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引用次数: 1

摘要

基于sram的FPGA由于其高性能,在当今的电子系统中已经成为一种流行的选择,并被大量应用。但是在辐射恶劣环境下,这些fpga需要一些附加的机制来应对软误差。现代fpga采用28nm技术,即使是组合电路也很容易受到软误差的影响。这种设计需要在其数据路径中设置软错误缓解电路。传统的软错误缓解技术,如三模冗余,是稳健的,但其面积开销是正常设计的三倍。本文提出了一种自动重复请求(ARQ)协议的变体,并结合延迟冗余来减少区域开销。合成结果表明,Cyclone II和Stratix II fpga的延迟分别提高了9.1和10%,资源利用率提高了1.94倍。我们的综合结果表明,我们的实现不仅在面积开销方面更好,而且如果在10个时钟周期内发生一次软错误,那么与TMR相比,所提议的体系结构的整体系统吞吐量更好。据我们所知,这是第一个实现基于ARQ协议的工作,利用延迟冗余来减轻基于sram的fpga中的软错误。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Towards low area overhead ARQ based soft error tolerant data paths for SRAM-based Altera FPGAs
The SRAM-based FPGA, due to their high performance, has become a popular choice in today's electronic systems and are used in large number of applications. But in radiation harsh environment these FPGAs require some additional mechanism to cope up with soft errors. Modern FPGAs are built in 28nm technologies, where even combinational circuits are substantially vulnerable to soft errors. Such designs require soft error mitigation circuits in their data paths. Conventional soft error mitigation techniques such as triple modular redundancy are robust but their area overhead is three times as compared to normal design. In this paper a variant of automatic repeat request (ARQ) protocol is proposed, along with delayed redundancy to reduce area overhead. Synthesis results show an improvement of 9.1 and 10% in latency for Cyclone II and Stratix II FPGAs, respectively, with a 1.94 times improvement in resource utilization. Our synthesis results show that our implementation is not only better in terms of area overhead but if a soft error occurs once in 10 clock cycles the overall system throughput is better for the proposed architecture compared to TMR. To our knowledge this is the first work to implement ARQ based protocol utilizing delayed redundancy to mitigate soft errors in SRAM-based FPGAs.
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