Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control

Abstract

A design method for an over-lOG-b/s buffer circuit for generating precise delay is proposed. A simple small-signal equivalent circuit model is introduced to investigate the delay characteristics of a current mode logic (CML) buffer circuit with load resistances. By setting the transconductance generator gm and output resistance in a MOSFET model as a function of drain current, the design equations for the delay and gain are derived. To confirm the validity of the design method, we fabricated buffer chain IC with the 65nm-MOSFET process and compared the measured and estimated delay. The errors between the measured and estimated delay are less than 15%, confirming the validity of the method.