Blocker and jitter tolerant wideband ΣΔ modulators

Abstract

Blocker and jitter sensitivity of continuous-time sigma-delta (CT-ΣΔ) converters is discussed. The interaction between blockers and clock jitter and its effect on the ADC resolution is also investigated. It is observed that out-of-band (OOB) blockers and clock jitter in the feedback DAC degrade the ADC resolution by convolving with the OOB quantization noise, thereby increasing the in-band noise floor. Some techniques on how to improve the blocker and jitter tolerance of CT-ΣΔ ADCs are outlined. It is verified that increased blocker tolerance relaxes the baseband channel filtering requirements in the signal path of a broadband receiver. By monitoring the internal signals of the ADC and dynamically controlling a front-end programmable gain amplifier, saturation and overload is avoided in the presence of strong interferers. The proposed blocker mitigation technique avoids changing the ADC internal loop parameters dynamically, resulting in fast settling time performance with moderate penalties in SNDR and circuit complexity.