Seventh International IEEE Conference on VLSI Multilevel Interconnection最新文献_第7页

Characterization of mechanical planarization processes 机械刨平过程的表征

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127844

P. Renteln, M.E. Thomas, J. M. Pierce

引用次数: 12

Non-destructive monitoring of planarization processes (CMOS technology) 平面化过程的无损监测(CMOS技术)

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127845

J. Teissier, A. Tissier, J. Eymery, J.C. Common, C. Mayet

引用次数: 0

Issues associated with the use of electroless copper films for submicron multilevel interconnections 与使用化学铜膜进行亚微米多层互连有关的问题

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127889

M.E. Thomas, Satoshi Sekigahama, S. A. Myers

{"title":"Issues associated with the use of electroless copper films for submicron multilevel interconnections","authors":"M.E. Thomas, Satoshi Sekigahama, S. A. Myers","doi":"10.1109/VMIC.1990.127889","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127889","url":null,"abstract":"Cu films between 1000 AA and 1 mu m thick were deposited from an electroless Cu plating bath on various metal seed layers. The bulk resistivity of Cu films was a function of the film thickness. For thin films of 1000 AA, the electrical resistivity was three times greater than reported bulk values. For 1- mu m films, resistivities of 2.3 mu Omega -cm were obtained. This larger resistivity is apparently influenced by defects grown into the film. The electrical and physical properties of these films were examined after rapid thermal processing at temperatures of up to 900 degrees C on inert substrates. Transmission electron microscope (TEM) analyses indicated changes in grain size from 600 AA to 2500 AA. Thin layers of FCC metals in contact with Cu, such as Ni or Pt, were detrimental to the electrical resistivity after moderate thermal processing. These interactions could be easily predicted from phase diagrams of Cu with other FCC metals and indicate that Ni encapsulation of Cu is impractical. Selective Cu deposition into dielectric channels on seed layers was found to be clean with little if any random field nucleation. Copper that was selectively deposited into contacts of a test gate array exhibited electrical continuity on CVD W but showed contact resistances substantially larger than standard metallurgies.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115820283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Electromigration in a two-level Al-Cu interconnection with W studs 带W螺柱的两级Al-Cu互连中的电迁移

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127852

T. Kwok, C. Tan, D. Moy, J. Estabil, H. Rathore, S. Basavaiah

引用次数: 10

The effect of CVD W/TiW metallization on very shallow CoSi/sub 2/ junctions CVD W/TiW金属化对极浅CoSi/sub 2/结的影响

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127884

S. Eshraghi, G. Georgiou, R. Liu

{"title":"The effect of CVD W/TiW metallization on very shallow CoSi/sub 2/ junctions","authors":"S. Eshraghi, G. Georgiou, R. Liu","doi":"10.1109/VMIC.1990.127884","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127884","url":null,"abstract":"The effect of Al/CVD W deposition on shallow junctions below CoSi/sub 2/ using 450-1800-AA sputtered TiW as a barrier/glue layer is investigated. The thermal stability of the Al/CVD W/TiW/CoSi/sub 2/ structure is studied by comparing the reverse bias current of the initial diodes with that after annealing the structure. The results for the deeper n/sup +/(P)/p diodes approximately 1000 AA below approximately 700-AA CoSi/sub 2/ are different from those for the p/sup +/(BF/sub 2/)/n diodes approximately 500 AA below CoSi/sub 2/. When the TiW is >450 AA thick, Al/CVD W does not degrade the n/sup +//p diodes. The reverse bias current is <10 nA/cm/sup 2/ when the Al/CVD W/900-AA TiW is annealed at up to 450 degrees C for 60 min. The n/sup +//p diode sport population increases when CVD W is deposited on 450-AA TiW. The diodes are severely degraded after 3000-AA Al is sputtered at 300 degrees C. The temperature of CVD W deposition affected the degradation of the p/sup +//n diodes. Higher-temperature depositions at approximately 500 degrees C degraded these diodes less than depositions at approximately 300 degrees C. However, annealing the Al/CVD W/900-AA TiW/CoSi/sub 2/ p/sup +//n structures at 400 degrees C for 30 min degrades the diodes independently of the CVD W temperature where 300>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133473595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

TiN production and performance as a barrier layer in ULSI technology TiN的生产及其在ULSI技术中作为阻挡层的性能

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127930

W.J. Kim, B. Kim, C.J. Lee, D. Harra

引用次数: 0

Evaluation of a heat-resistant photoimageable polyimide 耐热光成像聚酰亚胺的评价

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127908

R. Mo, T. Maw, A. Roza, K. Stefanisko, R. Hopla

{"title":"Evaluation of a heat-resistant photoimageable polyimide","authors":"R. Mo, T. Maw, A. Roza, K. Stefanisko, R. Hopla","doi":"10.1109/VMIC.1990.127908","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127908","url":null,"abstract":"A photosensitive, fully imidized, solvent-soluble polyimide system, Probimide 400, which demonstrates very broad processing latitudes in both photolithographic and thermal aspects is studied. A statistical experimental design was used to evaluate the effect of coating parameters on the coating quality of this system. This resulted in an optimal set of coating parameters for the best process latitude. Variables monitored were spin time, spin acceleration, spread cycle time, and exhaust velocity. Experiments at various spin speeds and solution viscosities using the refractive index as a probe supported the hypothesis that such high-molecular-weight polymers undergo chain alignment during the spin coating process. The degree of alignment depended on solution viscosity as well as spin speed. The photolithographic evaluation of Probimide 400 as a 5- mu m film showed a very broad exposure latitude, with less than +or-5% CD deviation for an 8- mu m structure over an exposed range of 75%. The effective dose, measured at 3675 nm, centers at 100 mJ/cm/sup 2// mu m of thickness. The material exhibits excellent thermal and tensile properties.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Multilevel interconnection and electrode separation technology using anodic oxidation and application to unidirectional surface acoustic wave transducers 利用阳极氧化的多级互连和电极分离技术及其在单向表面声波换能器上的应用

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127904

K. Yamanouchi, T. Meguro

引用次数: 0

Fabrication of polysilicon plugs for deep-submicron contact-holes 深亚微米接触孔用多晶硅插头的制造

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127924

J. Drynan, E. Ikawa, T. Kikkawa

引用次数: 1

Parasitic capacitance effects of the multilevel interconnects in DRAM circuits DRAM电路中多电平互连的寄生电容效应

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127915

J. Yuan, J. Liou

引用次数: 0