{"title":"Tungsten-titanium sputtering target processing effects on particle generation and thin film properties for VLSI applications","authors":"E. Waterman, J. Dunlop, T. Brat","doi":"10.1109/VMIC.1990.127887","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127887","url":null,"abstract":"The relationship between W-Ti target processing techniques, target structure, and deposited film quality is examined. Targets produced by three different methods are evaluated in terms of microstructure, purity, and their influence on the deposited film properties, with emphasis on film defect density. It is shown that the target manufacturing technique and the material purity have a significant impact on the defect density of the deposited films. Oxygen content as well as void pressure in the different targets can be assumed to be partly responsible for the observed results.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modelling fusible CVD glass planarization flow contours","authors":"L. White","doi":"10.1109/VMIC.1990.127903","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127903","url":null,"abstract":"A comparison between experimental and simulated fusible chemical vapor deposition (CVD) glass planarization flow contours is presented. The simulated contours assume Newtonian viscous flow and a hydrostatic pressure gradient caused by the surface tension and the radius of curvature of the contour. At long flow lengths, >or=100 mu m, reasonable agreement between experiment and simulation is obtained. Assuming no change in film surface tension, the flow rate constant increase is directly related to a tenfold decrease in film viscosity at the higher flow temperature.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"29 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117271933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Stress and TEM measurements as a function of temperature for aluminum alloys","authors":"D. Gardner, H. Longworth, P. Flinn","doi":"10.1109/VMIC.1990.127873","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127873","url":null,"abstract":"Measurements of the stress in situ as a function of temperature have proven to be an easy and powerful technique for obtaining information on the temperature and time for formation of both solid-state reactions and changes in morphology and structure. Correlating these changes using hot-stage transmission electron microscopy (TEM) and X-ray diffraction measurements has demonstrated that the stress changes correspond to chemical reactions and structural changes. The solid-state reactions of films consisting of aluminum with tantalum and vanadium were examined using stress measurements, TEM, X-ray diffraction, resistivity, and surface roughness measurements. The growth of very large gains (50-100 mu m) in Al/Cu/Cr films was also examined using both stress measurements and hot-stage TEM in situ during thermal cycling. Stress measurements revealed that aluminum reacts with vanadium first at 370 degrees C and then at 410 degrees C. Using X-ray diffraction and cross-sectional TEM analysis, the first reaction was found to correlate with the formation of VAl/sub 3/ and the second reaction with the formation VAl/sub 11/. The thickness of the vanadium aluminide layer changed significantly after the second reaction. Similar measurements of Al-Si/Ta revealed that an untextured jagged TaAl/sub 3/ layer forms at 430 degrees C.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128704229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced selective tungsten encapsulation of TiW capped aluminum interconnect","authors":"C.M. Dalton","doi":"10.1109/VMIC.1990.127879","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127879","url":null,"abstract":"With the use of the encapsulation barrier metal technique, the metal 1 thickness can be reduced due to the structure's high resistance to electromigration. With the thinning of metal 1, the thickness of the interlevel dielectric can be reduced within capacitance constraints with minimal concern for hillocking during the oxide deposition. With the thinning of metal 1, the interlevel deposition topography becomes more planar. This process enhancement permits the use of selective tungsten plugging of vias in that the tungsten fluorine barrier acts as a seed layer at the base of the via. This technique can be used in an n-level metalization process by repeating the metal 1 encapsulation process on subsequent metal interconnect levels.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129633091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Paulson, J. Klein, M. Woo, T. Kobayashi, R. Hendrix, E. Travis, F. Pintchovski, Y. See
{"title":"Manufacturable triple level metal technology for submicron CMOS","authors":"W. Paulson, J. Klein, M. Woo, T. Kobayashi, R. Hendrix, E. Travis, F. Pintchovski, Y. See","doi":"10.1109/VMIC.1990.127914","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127914","url":null,"abstract":"The triple-level-metal (TLM) module of a submicron CMOS technology with (titanium) salicided devices is discussed. The key technology features of the module include the use of conformal BPSG for enhanced planarization, a TiN barrier layer under M1, plasma-dry-tapered contacts and vias, and TiN antireflection coatings for metal patterning. Large-area test structures for each TLM component were used to develop and evaluate the processes. Electrical measurements and physical analysis are presented for these components.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"164 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114092303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Barrier metal effects on electromigration of layered aluminum metallization","authors":"H. Hoang, R. Coy, J. McPherson","doi":"10.1109/VMIC.1990.127856","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127856","url":null,"abstract":"An investigation was conducted of the electromigration (EM) in Al-1% Si, Al-1% Si-0.5% Cu, and Al-2% Cu films with Ti:W and CVD-W barrier metals. The EM test results indicate that the rough surface texture of the underlying CVD-W layer degrades the electromigration performance of the Al-1% Si and Al-1% Si-0.5% Cu films. However, the EM performance of Al-2% Cu multilayered metallization was found to be independent of the barrier metal type. The failure kinetics of multilayered metallization was studied by investigating the resistance rise mechanism. The resistance rise during EM testing of CVD-W/Al-1% Si-0.5% Cu and Ti:W/Al-1% Si-0.5% Cu seems to be well behaved and follows a power law dependence.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"81 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114327711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Whitwer, D. Milligan, J. Garner, S. Sun, M. Shenasa, T. Davies, C. Lage
{"title":"A submicron, double level metal process for high density memory applications","authors":"F. Whitwer, D. Milligan, J. Garner, S. Sun, M. Shenasa, T. Davies, C. Lage","doi":"10.1109/VMIC.1990.127842","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127842","url":null,"abstract":"A process is described that was developed for application to a 1-Mb SRAM product. This highly reliable, very dense interconnect process features tungsten metal-1 and spin-on-glass (SOG) etchback planarization. The tungsten metal layer provides excellent step coverage with good electromigration resistance. The tungsten patterning process results in very little etch bias and anisotropic etch profiles. Details relating to both metallization and planarization are discussed. The results of electrical characterization and reliability testing are presented.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127599447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardening process for plasma deposited planar amorphous carbon films used in bilayer resists","authors":"S. Pang, R. B. Goodman, M. Horn","doi":"10.1109/VMIC.1990.127922","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127922","url":null,"abstract":"A dry planarization process has been developed to produce planar amorphous carbon (a-C:H) films. These films provide a high degree of planarization over large distances, and they can be deposited at room temperature with low ion bombardment energy (10 V) and high deposition rate (300 nm/min). Depending on the deposition conditions and subsequent processing requirements, a hardening step may be needed. Various degrees of hardness can be obtained by heating the samples and/or exposing them to a low-power plasma. One effective hardening process is to expose the films to a low-power N/sub 2/ discharge (5-mW/cm/sup 2/ RF power and -10-V DC bias voltage) at 150 degrees C and 500 mtorr for 30 min. Excimer laser projection lithography has been used to define submicrometer patterns in bilayers which consist of a wet or dry deposited inorganic photoresist applied on top of the planarization layers.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126568360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Resistless patterning of aluminum","authors":"T. Cacouris, R. Scarmozzino, R. Osgood","doi":"10.1109/VMIC.1990.127876","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127876","url":null,"abstract":"A technique for patterning and depositing aluminum using laser-assisted selective chemical vapor deposition (CVD) is presented. This is accomplished using a light-assisted process that activates an adsorbed metallorganic precursor for aluminum, dimethyl-aluminum hydride (DMAlH), onto the substrate surface, thus forming a seed layer for subsequent selective CVD. In the same processing chamber, once the patterning is delineated via this seed layer, the substrate temperature is raised to 110-180 degrees C, and selective CVD of aluminum takes place. A report is presented on the issues of selectivity, growth rates, morphology, electrical properties, and elemental composition of aluminum grown in this manner. Electrical resistivity, for example, can be as low as twice that of bulk aluminum. Furthermore, in order to make such a process compatible with multilevel metallization schemes, contact resistivity of such a film to preexisting aluminum metallization (with a native aluminum oxide) was measured and found to be approximately 0.2 mu Omega -cm/sup 2/ without any special pre- or post-treatment. Previous attempts at such a deposition and patterning scheme were less than successful at obtaining reliably low contact resistivities.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115847576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mechanism of AC electromigration","authors":"K. Shono, T. Kuroki, H. Sekiya, N. Yamada","doi":"10.1109/VMIC.1990.127851","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127851","url":null,"abstract":"A model for the mechanism of AC electromigration based on the thermal response of Al stripes is proposed. The model is based on the temperature difference between the positive period and the negative period. The thermal time constant of the Al stripe, underlying SiO/sub 2/, and Si substrate is on the order of microseconds and that of the package and ambient is a few seconds. When the cycle time of the current is longer than thermal time constant, the temperature of the Al stripes obeys the current waveform. When the cycle time is shorter than the thermal time constant, the temperature keeps constant. Mean time to failure (MTF) depends on the temperature according to Arrhenius's equation. The temperature difference between positive and negative periods causes an unbalance of atomic flux between the periods. Thus, open-circuit failure can take place under AC conditions.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114977407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}