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Seventh International IEEE Conference on VLSI Multilevel Interconnection最新文献

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Design guidelines for deep-sub-micrometer interconnections 深亚微米互连的设计准则
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127916
Y. Ushiku, H. Kushibe, H. Ono, A. Nishiyama
{"title":"Design guidelines for deep-sub-micrometer interconnections","authors":"Y. Ushiku, H. Kushibe, H. Ono, A. Nishiyama","doi":"10.1109/VMIC.1990.127916","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127916","url":null,"abstract":"Design guidelines for deep-submicrometer interconnections are proposed. Wiring capacitance, interconnection delays, and crosstalk noise were simulated using a three-dimensional capacitance simulator and SPICE, in order to define such interconnection parameters as the thickness and material of the conductors and insulators and the ratio of line width to spacing. Based on this analysis, it is recommended that the aspect ratio be less than one. The importance of low-resistivity metals at sub-half-micrometer dimensions is also demonstrated. The extreme limit for interconnections does not extend very far beyond 0.2 mu m, so a new design concept will be needed for deep-submicrometer VLSI circuits.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125879715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Filling of contacts and interconnects with Cu by XeCl laser reflow 用XeCl激光回流填充触点和连接处的铜
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127921
S.-Q. Wang, E. Ong
{"title":"Filling of contacts and interconnects with Cu by XeCl laser reflow","authors":"S.-Q. Wang, E. Ong","doi":"10.1109/VMIC.1990.127921","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127921","url":null,"abstract":"The process window for XeCl laser ( lambda =308 nm) induced reflow of sputter-deposited Cu film to planarize and fill 1- mu m-diameter contacts and 1- mu m-wide interconnect trenches in a 1- or 2- mu m-thick BPSG layer was investigated at room temperature, 365 degrees C, and 440 degrees C. Complete filling of 1- mu m contacts and trenches with an aspect ratio of 1 is possible with an appreciable process window, but filling of these same contacts and trenches with an aspect ratio of 2 is only possible at a substrate temperature of 440 degrees C. The properties of the Cu films, such as sheet resistance, reflectance, grain size, and stress, were also characterized as a function of laser fluence at room temperature, 365 degrees C, and 440 degrees C.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131351556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Application of BSG films as interlevel dielectric in a 1 mu m DLM process BSG薄膜作为层间介质在1 μ m DLM工艺中的应用
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127909
A. Rey, P.Y. Lesaicherre, E. Pourquier
{"title":"Application of BSG films as interlevel dielectric in a 1 mu m DLM process","authors":"A. Rey, P.Y. Lesaicherre, E. Pourquier","doi":"10.1109/VMIC.1990.127909","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127909","url":null,"abstract":"Summary form only given. Borosilicate glass (BSG) films were deposited in an atmospheric-pressure chemical vapor deposition (CVD) system. The best step coverage capabilities of BSG films were obtained for a 5% boron concentration and an oxygen/hydride ratio of 70/1. In these process conditions, various BSG film thicknesses were deposited on test structures composed of metal lines with different spacings, thicknesses, and sidewall profiles. The step coverage results are plotted on dimensionless diagrams. The limit curve of void formation and abacus of equal lateral step coverage are shown for two metal profiles. The planarization of the BSG films, realized by etchback with a spin-on-glass (SOG) layer, was studied on test structures. With any BSG thicknesses or etchback quantities, a planarization with a total SOG sacrificial layer without void formation is possible only when the aspect ratio is lower than the previous limit. A BSG interlevel dielectric (ILD) was determined for a 1- mu m DLM process by using the dimensionless diagrams and considering the highest aspect ratios of the technology. Electrical characterization results confirm the good planarization capability of the BSG ILD.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122232094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low temperature interlayer formation technology using a new siloxane polymer film 采用新型硅氧烷聚合物薄膜的低温层间形成技术
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127862
M. Suzuki, T. Homma, Y. Numasawa
{"title":"Low temperature interlayer formation technology using a new siloxane polymer film","authors":"M. Suzuki, T. Homma, Y. Numasawa","doi":"10.1109/VMIC.1990.127862","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127862","url":null,"abstract":"A new technology for low-temperature dielectric film formation under Al wirings is described. This technology utilizes spin-on film formed from the organic siloxane polymer solution optimized to have minimal film shrinkage/stress generation during heat treatment. The optimized solution is composed of 62-mol.% tetra-ethoxy-silane (Si(OEt)/sub 4/), 31-mol.% methyl-tri-ethoxy-silane (Me-Si(OEt)/sub 3/), and 7-mol.% phosphorus-triethoxide (PO(OEt)/sub 3/) oligomer in ethyl alcohol. Crack-free thick siloxane polymer film with no carbon is formed by three-step heat treatment processes (150 degrees C hot plate baking, 400 degrees C furnace annealing in N/sub 2/, and 800 degrees C furnace annealing in O/sub 2/). The planarization capability of this film is superior to that of the conventional BPSG reflow film, and other film properties are as good as those of the CVD-PSG film.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"34 9-10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120918971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The mechanical planarization of interlevel dielectrics for multilevel interconnect applications 用于多电平互连应用的层间介质的机械平面化
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127923
M.E. Thomas, Satoshi Sekigahama, P. Renteln, J. M. Pierce
{"title":"The mechanical planarization of interlevel dielectrics for multilevel interconnect applications","authors":"M.E. Thomas, Satoshi Sekigahama, P. Renteln, J. M. Pierce","doi":"10.1109/VMIC.1990.127923","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127923","url":null,"abstract":"A description is given of the application of mechanical planarization to the interlevel dielectric (ILD) of a multilevel interconnect system. Experimental results obtained from large 80K, two-level metal CMOS gate arrays (0.7 cm/sup 2/) having mechanically planarized ILD indicated leveling lengths on the order of 0.5 cm and excellent via functionality. Surface leveling with variations of less than 200 AA was readily achieved over the whole gate array die. No detrimental effects were observed in a fully functional die when compared with devices using sacrificial spin-on glass. The results of this study indicate that mechanical planarization will make a critical contribution to the fabrication of ULSI devices having 0.25- mu m interconnect feature sizes.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115829522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The incorporation of copper in CVD aluminum by diffusion from in-situ sputtered sources 原位溅射源扩散铜在CVD铝中的掺入
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127878
L. Kwakman, D. Huibregtse, H. Piekaar, E. Granneman, K. Cheung, C. Case, W. Lai, R. Liu, R. J. Schutz, R. Wagner
{"title":"The incorporation of copper in CVD aluminum by diffusion from in-situ sputtered sources","authors":"L. Kwakman, D. Huibregtse, H. Piekaar, E. Granneman, K. Cheung, C. Case, W. Lai, R. Liu, R. J. Schutz, R. Wagner","doi":"10.1109/VMIC.1990.127878","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127878","url":null,"abstract":"It is demonstrated that in-situ sputtered Cu-containing films serve as excellent diffusion sources for chemical vapor deposited (CVD) Al at temperatures as low as 230 degrees C. Pure Cu, Al-2 wt.% Cu, and Al-0.5 wt.% Cu were used as the source film. Rutherford backscattering spectroscopy (RBS) was used to determine the film grain structures. It was found that the diffusion of Cu from the in-situ Cu-Al film is unhindered by the CVD process and reaches a concentration approximately that of the solid solubility in the CVD Al. A maximum of 0.37 wt.% of the Cu is incorporated into the CVD film from a sputtered pure Cu source. This should provide adequate electromigration resistance for the CVD Al.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"237 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123888208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Electromigration resistance of TiN-layered Ti-doped Al interconnects tin层状掺钛铝互连的电迁移电阻
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127897
E.M. Atakov
{"title":"Electromigration resistance of TiN-layered Ti-doped Al interconnects","authors":"E.M. Atakov","doi":"10.1109/VMIC.1990.127897","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127897","url":null,"abstract":"The electromigration performance of 2- mu m-wide, 17-mm-long single-layer and TiN-layered Al interconnects was studied. Al-1%Si-0.15%Ti and Al-0.15%Ti-based films were sputter deposited at 200-300 degrees C and 475 degrees C substrate temperatures, respectively. The interconnect lifetime improved dramatically when Al-0.15% Ti alloy was used instead of Al-1%Si-0.15%Ti. A TiN underlayer reduced the Al alloy EM resistance, except when the TiN was exposed to air prior to Al deposition.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131478412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An advanced four level interconnect enhancement module for 0.9 micron CMOS 一个先进的四电平互连增强模块0.9微米CMOS
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127838
C. A. Bollinger, D. Grube, S. Lytle, E. Martin, J.A. Shimer, H. R. Siddiqui
{"title":"An advanced four level interconnect enhancement module for 0.9 micron CMOS","authors":"C. A. Bollinger, D. Grube, S. Lytle, E. Martin, J.A. Shimer, H. R. Siddiqui","doi":"10.1109/VMIC.1990.127838","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127838","url":null,"abstract":"A four-level metal interconnect enhancement has been developed for the AT&T Twin-Tub(V) 0.9- mu m CMOS technology. The interconnect process includes resist etchback planarization at all dielectric levels, tungsten plugs for window fill, and a bilayer metal structure of Al-Cu/Ti:W for interconnection. The design rules include frameless contacts, stacked windows, and the maintenance of constant design rules throughout all four levels. Process details are described and electrical results are presented on the four-level metal enhancement. Electrical results include isolation, continuity, contact resistance, junction leakage, and transistor aging. The 0.9- mu m CMOS n-channel and p-channel transistors exhibit no changes in parametric behavior due to the four-level metal interconnect process. Using the four-level interconnect enhancement results in a reduction of active chip area of up to 40% in AT&T's 0.9- mu m standard-cell ASIC technology.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128085701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Electrical characterization of doped and undoped PECVD TEOS oxides 掺杂和未掺杂PECVD TEOS氧化物的电学特性
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127907
J. Butler, G. Allen, A. Hall, R. Nowak
{"title":"Electrical characterization of doped and undoped PECVD TEOS oxides","authors":"J. Butler, G. Allen, A. Hall, R. Nowak","doi":"10.1109/VMIC.1990.127907","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127907","url":null,"abstract":"It is shown that charge in plasma-enhanced chemical vapor deposition (PECVD) TEOS-based films is generated as a result of high-temperature annealing. This effect is dependent on oxide type and can be greatly reduced by the use of good-quality USG barrier layer or reduction of the anneal temperature. However, at very high temperatures the amount of generated charge is substantial. It was found that neither the use of TEOS as a precursor nor plasma processing is independently detrimental to the levels of charge in the oxides. The analytical data show some buildup of impurities at the Si-SiO/sub 2/ interface. Although impurity concentrations are comparable to those of the other oxides tested, this does not preclude the possibility of interactions of the plasma field with impurities to influence the fixed charge. The thermal energy of the postdeposition cycle above 875 degrees C may be high enough to cause redistribution of ions and/or activation of species that are not detected electrically in as-deposited films. The charge observed is most likely localized close to the Si-SiO/sub 2/ interface and seems proportional to the length of plasma exposure.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"411 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132341862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Laser planarization of AlSiCu on various barrier metals for VLSI 超大规模集成电路中AlSiCu在各种阻挡金属上的激光平面化
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127925
C. Yu, T. Doan, S. Kim
{"title":"Laser planarization of AlSiCu on various barrier metals for VLSI","authors":"C. Yu, T. Doan, S. Kim","doi":"10.1109/VMIC.1990.127925","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127925","url":null,"abstract":"Laser planarization of AlSiCu film on diffusion barriers of Ti/RTA TiN, Ti, RTA TiN, reactive TiN/Ti, and TiW was investigated to determine the effect of the barrier layer on the process window and junction integrity. While the process window did not vary significantly for various diffusion barriers investigated, each barrier scheme showed a different degree of effectiveness in preserving the junction integrity during laser processing. In addition, for a given diffusion barrier scheme, the junction integrity was found to depend on the substrate temperature and optical fluence.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133452583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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