Seventh International IEEE Conference on VLSI Multilevel Interconnection最新文献_第3页

Quantitative measurement of the moisture content in thin films 薄膜中水分含量的定量测量

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127918

J. N. Cox, G. Shergill, M. Rose, J. Chu

{"title":"Quantitative measurement of the moisture content in thin films","authors":"J. N. Cox, G. Shergill, M. Rose, J. Chu","doi":"10.1109/VMIC.1990.127918","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127918","url":null,"abstract":"A description is given of the modification and application of a moisture evolution analyzer to quantitatively measure the moisture content of thin-film dielectrics used in VLSI manufacture. The development of computerized acquisition of moisture, temperature, and time data permits adsorbed water to be distinguished from more tightly bound absorbed water. The incorporation of a computer-driven temperature controller and a 7-in.-diameter crucible furnace allows the moisture evolution characteristics of thin films on 150-mm-diameter wafers to be studied under a wide variety of temperature cycles and ramps up to 1000 degrees C. Studies of thermal oxides, plasma oxides, spin-on-glass, and CVD doped and undoped oxides show moisture contents from less than 0.01 wt.% to in excess of 10 wt.% water, demonstrating the sensitivity and range of the technique. The results for borophosphosilicate glass (BPSG) thin films as a function of doping levels are presented. The moisture in these films was found to be partitioned approximately equally between adsorbed and absorbed moisture. As the doping levels (wt.%B/wt.%P) were varied from 0/4.2 to 2.5/3.8, the moisture content varied by 30%. The effects of low-temperature heat treatments and alternative deposition chemistries are also discussed.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129610315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Planarization for 0.5 mu m CMOS/BiCMOS technology 平面化0.5 μ m CMOS/BiCMOS技术

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127927

P. Pai

引用次数: 0

A via failure mode in electromigration of multilevel interconnect 多层互连电迁移中的通孔失效模式

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127857

N. Bui, V. Pham, J. Yue, D.L. Wollesen

引用次数: 5

Effect of barrier metal under first aluminum layer on reliability of interconnect vias and contact 第一层铝层下阻挡金属对互连过孔和接触可靠性的影响

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127900

T. Wada, I. Matsuo, T. Umemoto

引用次数: 2

Low stress oxide/nitride passivation topography and influence on electrical devices 低应力氧化氮钝化形貌及其对电气器件的影响

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127906

K. Menz, R. Braun, W. Henkel, R. Huber, B. Neureither, O. Spindler, H. Treichel

引用次数: 0

Integrated deposition and etchback of tungsten in a multi-chamber, single-wafer system 钨在多腔、单晶圆系统中的集成沉积和蚀刻

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127936

T. Clark, P. E. Riley, M. Chang, S. Ghanayem, C. Leung, A. Mak

引用次数: 2

Sub-atmospheric chemical vapor deposition (SACVD) of TEOS-ozone USG and BPSG teos -臭氧USG和BPSG的亚大气化学气相沉积(SACVD)

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127910

P. Lee, M. Galiano, P. Keswick, J. Wong, B. Shin, D. Wang

引用次数: 7

Advances in production methods in VLSI and ULSI technology using isolated-chamber sputter deposition of Al 1% Si films 利用隔离室溅射沉积Al - 1% Si薄膜的VLSI和ULSI技术生产方法的进展

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127886

Y. Ahn, C. Oh, W. Hwang, J. Koh, Y. Song, G. S. Cho, C. Ko, D. Harra, Y.K. Kim, J. van Gogh, C. Shin

{"title":"Advances in production methods in VLSI and ULSI technology using isolated-chamber sputter deposition of Al 1% Si films","authors":"Y. Ahn, C. Oh, W. Hwang, J. Koh, Y. Song, G. S. Cho, C. Ko, D. Harra, Y.K. Kim, J. van Gogh, C. Shin","doi":"10.1109/VMIC.1990.127886","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127886","url":null,"abstract":"Sputtering process optimization is described as related to steady-state production of VLSI and ULSI devices using isolated deposition modules in a production environment. Improvements in step coverage for Al-1%-Si, obtained over VLSI and ULSI level topology typical of 1-Mb to 16-Mb semiconductor devices, are described, and data are presented. Techniques for improving the average step coverage and the worst-case step coverage over 1- mu m-thick BPSG contact openings are discussed. The process improvements require the use of isolated processing chambers for specific processing steps in the appropriate chambers. By taking advantage of the isolated processing chambers and fine tuning various process settings, the worst-case step coverage was improved from 25 to 40% for a typical VLSI topology. These techniques were also effective in reducing step coverage over opposing contact-opening sidewalls across the wafer. The factors and deposition conditions responsible for these improvements are presented. Corresponding data on grain size and silicon nodule size as a function of deposition conditions after contact alloy are presented.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115434824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low resistance epitaxial CoSi/sub 2/-contacts for VLSI circuits 用于VLSI电路的低电阻外延CoSi/sub 2/-触点

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127932

C. Adamski, D. Uffmann, S. Meiser, L. Niewohner, C. Schaffer

引用次数: 0

A high performance, four metal layer interconnect system for bipolar and BiCMOS circuits 一种用于双极和BiCMOS电路的高性能四金属层互连系统

Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127841

S. Wilson, J. Freeman, C. Tracy

引用次数: 4