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Seventh International IEEE Conference on VLSI Multilevel Interconnection最新文献

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Unifying model for step coverage in deposition processes for multilevel interconnection 多层互连沉积过程阶跃覆盖的统一模型
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127868
G. Raupp, T. Cale
{"title":"Unifying model for step coverage in deposition processes for multilevel interconnection","authors":"G. Raupp, T. Cale","doi":"10.1109/VMIC.1990.127868","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127868","url":null,"abstract":"A molecular transport-reaction model based on a pseudosteady approximation of the Boltzmann equation provides a unifying understanding of step coverage phenomena observed for the spectrum of deposition processes. The model suggests that for all chemically based processes, the reactivity of precursors or intermediates, as characterized by their reactive sticking coefficients, controls step coverage. Classical reaction rate expressions may be used to estimate reactive sticking coefficient dependences on flux; these dependences are directly incorporated in the model to determine the spatial and temporal evolution of the sticking coefficients as the feature fill proceeds. For all but first-order reactions, use of a single value for the sticking coefficient is not warranted. The model is formulated in such a way that physical properties of the films (i.e. density) can be estimated if the property dependence on precursor incident angle is known.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125177450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Experimental study of metal-metal contact properties using spin on glass 玻璃上自旋金属-金属接触特性的实验研究
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127926
R. Wolters, W. Heesters
{"title":"Experimental study of metal-metal contact properties using spin on glass","authors":"R. Wolters, W. Heesters","doi":"10.1109/VMIC.1990.127926","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127926","url":null,"abstract":"Degassing data of cured spin-on glass (SOG) layers and wafer temperature measurements during the sputter etch process are given. A solution for the metal-metal contact problem using an in situ preheat step prior to a (soft) sputter etch process and subsequent metal deposition is presented. An improvement in IN-INS contact string resistance yield from approximately 40% to 99.5% could be achieved in this process.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125031006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of underlayer on sputtered aluminum grain structure and its correlation with step coverage in submicron vias 衬底层对溅射铝晶粒结构的影响及其与亚微米孔中台阶覆盖度的关系
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127888
D. Pramanik, V. Jain
{"title":"Effect of underlayer on sputtered aluminum grain structure and its correlation with step coverage in submicron vias","authors":"D. Pramanik, V. Jain","doi":"10.1109/VMIC.1990.127888","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127888","url":null,"abstract":"Summary form only given. The grain size and intragrain roughness of aluminum films has been studied for various underlayers under the same deposition conditions. Intragrain roughness is shown to correlate with breaks in Al step coverage on via sidewalls. It is concluded that the best step coverages will be obtained for those underlayers and deposition conditions which produce the minimum intragrain roughness.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131727934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of laser planarized second aluminum for semiconductor devices 半导体器件用激光平面化二次铝的评价
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127849
B. Boeck, K. Fu, F. Pintchovski, N. Crain, S. Chen, H. Chu
{"title":"Evaluation of laser planarized second aluminum for semiconductor devices","authors":"B. Boeck, K. Fu, F. Pintchovski, N. Crain, S. Chen, H. Chu","doi":"10.1109/VMIC.1990.127849","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127849","url":null,"abstract":"Laser planarization was applied to the second layer of metallization of a static memory part. Electrical evaluation by means of chain resistance, contact chain resistance, metal continuity/shorts, and leakage showed no deleterious effect for the laser planarized parts when compared to the control split, while SEM cross-sections showed fully planarized vias and large grain size for the metal. An electromigration study conducted to evaluate the effect of laser planarization on reliability indicated that an improvement in electromigration resistance, as compared to the control split, is attained when the metal is submitted to laser planarization.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122290651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Finite element numerical modeling of currents in VLSI interconnects VLSI互连电流的有限元数值模拟
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127858
A. Enver, J. Clement
{"title":"Finite element numerical modeling of currents in VLSI interconnects","authors":"A. Enver, J. Clement","doi":"10.1109/VMIC.1990.127858","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127858","url":null,"abstract":"Three-dimensional finite-element modeling has been used to simulate density distributions in filled-via structures. Peak current density in a single filled via was studied as a function of the direction of the current path, resistivity of the via-filled material, metal overlap of the via, and misalignment. Simulations were also carried out to examine the effects of the direction of the current flow and the resistivity of the via-fill material on the distribution of current in multiple vias.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128336771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Formation of tungsten MOS gate structures using an integrated RTO/PVD process 采用集成RTO/PVD工艺形成钨MOS栅极结构
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127891
C. B. Cooper, M. Delfino, J. Fair, S. Felch, D. Hodul, R. McFarland
{"title":"Formation of tungsten MOS gate structures using an integrated RTO/PVD process","authors":"C. B. Cooper, M. Delfino, J. Fair, S. Felch, D. Hodul, R. McFarland","doi":"10.1109/VMIC.1990.127891","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127891","url":null,"abstract":"Tungsten metal gate structures formed with air exposure between the process steps were compared to those formed using integrated sequences where the wafer was passed in vacuum (1E-7 torr) between steps. The wafers used were 150-mm, <100>, p-type silicon with bulk resistivity of 3-9 Omega -cm. All oxidations were done within 15 min of the HF dip used to remove the native oxide. Tungsten metal capacitors formed on thin silicon dioxide showed improvement in breakdown field and fixed oxide charge density when the samples were handled under vacuum between the oxidation and metal deposition steps. Annealing after metal deposition lowered the sheet resistance of the film as well as the fixed oxide charge density.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132912598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of critical wiring structures using CAPCAL V1.3 使用CAPCAL V1.3分析关键布线结构
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127912
A. Seidl, P. Seegebrecht, M. Schreil
{"title":"Analysis of critical wiring structures using CAPCAL V1.3","authors":"A. Seidl, P. Seegebrecht, M. Schreil","doi":"10.1109/VMIC.1990.127912","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127912","url":null,"abstract":"Two basic features of modern VLSI technology necessitate the three-dimensional (3D) solution of electrical field problems: (1) the lateral feature size is of the same order of magnitude as typical layer thicknesses; and (2) increasing layout complexity gives rise to structures for which only a genuine 3D description is applicable. The package CAPCAL V1.3 constitutes an improved version of the program introduced by A. Seidl et al. (1988). A particular extension of V1.3 is the capability for resistance calculations. As examples of the application of CAPCAL, 3D analysis of nonplanar line crossings and contact hole resistance measurement are shown.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of titanium addition to copper interconnect on electromigration open circuit failure 铜互连中添加钛对电迁移断路的影响
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127896
K. Hoshino, H. Yagi, H. Tsuchikawa
{"title":"Effect of titanium addition to copper interconnect on electromigration open circuit failure","authors":"K. Hoshino, H. Yagi, H. Tsuchikawa","doi":"10.1109/VMIC.1990.127896","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127896","url":null,"abstract":"The effect on electromigration open-circuit failure of the addition of a small amount of titanium into copper interconnects is investigated. Mean time to failure (MTF) increased with increasing Ti concentration up to somewhere around 0.4 wt.% and decreased sharply by further addition of Ti, while the resistivity of Cu-Ti films increased monotonically with increasing Ti concentration. Cu-0.37wt.%Ti interconnect had a two-orders-of-magnitude larger MTF than pure Cu interconnect and had a low resistivity of 2.7 mu Omega -cm, which was as low as the resistivity of pure aluminum interconnects. Grain size was drastically reduced by Ti addition and was independent of Ti concentration. When the Ti content in Cu exceeded the solubility limit (0.5 wt.% at 450 degrees C), formation of a Cu-Ti compound was indicated by X-ray diffraction. Although the exact Ti concentration involved is uncertain, the small content of Ti in Cu interconnects improved the MTF unless the Cu-Ti compound was not formed. The formation of the Cu-Ti compound caused deterioration of the electromigration resistance.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115205874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A new caged structure spin-on-silica for multilevel interconnect application 用于多级互连的新型笼状硅自旋结构
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127863
R. Pineda, C. Chiang, D. Fraser
{"title":"A new caged structure spin-on-silica for multilevel interconnect application","authors":"R. Pineda, C. Chiang, D. Fraser","doi":"10.1109/VMIC.1990.127863","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127863","url":null,"abstract":"A unique, carbon-free silica material, based on a new concept of converting caged (HSiO/sub 3/2/)/sub n/ structures by eliminating the hydrogens and cross-linking the caged structures with oxygen, was characterized for ILD (interlayer dielectric) applications. The films show excellent uniformity as well as good planarity. At temperatures below 600 degrees C, no volume shrinkage is observed. However, above this temperature, volume losses of as much as 30% can be observed. FTIR (Fourier transform infrared) spectroscopy data and film stress measurements (used to determining film stability) show that a stable crack-free oxide (SiO/sub 2/) can be obtained with a high-temperature oven bake or with an optimized process combining low-temperature oven baking and exposure to oxygen plasma. These early results show that this spin-on-silica precursor is suitable for nonetchback processes such as those that involve oxide deposition between polysilicon and the first level of metal. With processing improvements at lower temperatures, the precursor also shows promise for intermetal oxide applications.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115992937","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Step coverage study of PETEOS deposition for intermetal dielectric applications 金属间介电材料PETEOS沉积的阶梯覆盖研究
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127861
D. Yu, D. Favreau, E. Martin, A. Manocha
{"title":"Step coverage study of PETEOS deposition for intermetal dielectric applications","authors":"D. Yu, D. Favreau, E. Martin, A. Manocha","doi":"10.1109/VMIC.1990.127861","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127861","url":null,"abstract":"A simple one-step plasma-enhanced chemical vapor deposition of TEOS (PETEOS) deposition process for submicron multilevel metallization has been developed. The effect of deposition conditions on PETEOS step coverage and deposition profile is investigated. Two new processes are demonstrated which meet the step coverage requirements for 0.6- mu m technology. The first process produces a directional deposition profile using relatively low pressure and high TEOS to oxygen flow. The second process utilizes the addition of NF/sub 3/ to achieve a favorable dielectric profile.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132319266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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