发布求助
文献互助 智能选刊 最新文献

Seventh International IEEE Conference on VLSI Multilevel Interconnection最新文献

筛选
英文 中文
Copper-parylene interactions in multilevel interconnection structures 多层互连结构中的铜-聚对二甲苯相互作用
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127892
J. F. Mcdonald, S. Dabral, G-R. Yang, H. Bakhru, T. Lu
{"title":"Copper-parylene interactions in multilevel interconnection structures","authors":"J. F. Mcdonald, S. Dabral, G-R. Yang, H. Bakhru, T. Lu","doi":"10.1109/VMIC.1990.127892","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127892","url":null,"abstract":"Copper is investigated as an interconnect metal and parylene as the interlayer dielectric. It has been found that copper adheres to the parylene well. The effect of a soldering step has been simulated by annealing. Using Rutherford backscattering (RBS) and secondary ion mass spectroscopy (SIMS) it has been found that copper does indeed diffuse into the parylene at elevated temperatures. However, this diffusion is small and does not affect the dielectric leakage properties much.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127226017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Formation of self-aligned TiN/CoSi/sub 2/ bilayer from Co/Ti/Si and its applications in salicide, diffusion barrier and contact fill Co/Ti/Si自对准TiN/CoSi/sub - 2/双分子层的形成及其在杀盐剂、扩散势垒和接触填充中的应用
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127871
C. Wei, D. Fraser, M. Dass, T. Brat
{"title":"Formation of self-aligned TiN/CoSi/sub 2/ bilayer from Co/Ti/Si and its applications in salicide, diffusion barrier and contact fill","authors":"C. Wei, D. Fraser, M. Dass, T. Brat","doi":"10.1109/VMIC.1990.127871","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127871","url":null,"abstract":"A self-aligned TiN/CoSi/sub 2/ structure was formed from Co/Ti/Si; this scheme is compatible with salicide technology. Low contact/diffusion resistances and good device characteristics were obtained using this method. In addition, the TiN overlayer can be used for the diffusion barrier in between Al and CoSi/sub 2/ and for dopant diffusion. The dopant diffusion barrier permits the use of in-situ n/sup +//p/sup +/ doped selective Si plugs for contact filling. The TiN also improves the temperature stability of the underlying CoSi/sub 2/ film.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126575680","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Selective and blanket tungsten interconnection and its suitability for 0.2-micron ULSI 选择性和毯状钨互连及其对0.2微米ULSI的适用性
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127870
T. Ohba, M. Shirasaki, N. Misawa, T. Suzuki, T. Hara, Y. Furumura
{"title":"Selective and blanket tungsten interconnection and its suitability for 0.2-micron ULSI","authors":"T. Ohba, M. Shirasaki, N. Misawa, T. Suzuki, T. Hara, Y. Furumura","doi":"10.1109/VMIC.1990.127870","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127870","url":null,"abstract":"Voids and nondeposition were observed in via holes using blanket W and sputter Al because step coverage was significantly affected by the uniformity of the glue layer and by shadowing. In studying integrated multiple metallization (IMM), it was found that selective W adequately fills via holes down to 0.2 mu m in diameter and greatly improves step coverage, with optimum coverage even after 40% via-hole filling. Blanket W and Al wiring can thus be used for high-aspect via holes, even if step coverage is poor. The contact resistance of selective W to poly-Si is lower than that of Al/TiN in 0.2- mu m contacts. Thus, metallization based on selective W satisfies interconnection requirements in gigabit-scale integration.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121479031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Dielectric film influence on stress-migration 介质膜对应力迁移的影响
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127898
A. Isobe, K. Okamura, S. Ogura, O. Mizuno
{"title":"Dielectric film influence on stress-migration","authors":"A. Isobe, K. Okamura, S. Ogura, O. Mizuno","doi":"10.1109/VMIC.1990.127898","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127898","url":null,"abstract":"The purpose of this work is to clarify the relation between dielectric film characteristics and stress migration (SM). It has been considered that the dielectric-deposition-temperature-induced stress, caused by the difference of the expansion coefficients for Al, is the main factor for SM. However, it was found that Al diffusion into dielectrics, Al recrystallization, and dielectrics flexibility are also significant for SM. It is shown that the best method of dielectrics formation against SM is depositing low-Al-diffusivity dielectrics at low temperature after stress relaxation.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115414907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved CVD aluminum deposition using in-situ sputtered nucleation layers 原位溅射成核层改进CVD铝沉积
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127881
K.P. Cheung, C. Case, R. Liu, R. J. Schutz, R. Wagner, L. Kwakman, D. Huibregtse, H.W. Piekaar, E. Granneman
{"title":"Improved CVD aluminum deposition using in-situ sputtered nucleation layers","authors":"K.P. Cheung, C. Case, R. Liu, R. J. Schutz, R. Wagner, L. Kwakman, D. Huibregtse, H.W. Piekaar, E. Granneman","doi":"10.1109/VMIC.1990.127881","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127881","url":null,"abstract":"Superior-quality chemical vapor deposited (CVD) Al films have been achieved using tri-isobutylaluminum (TIBA) on in-situ sputtered nucleation layers. The nucleation layer enhances the growth of CVD Al, resulting in smooth, high-quality films suitable for VLSI application. The use of in-situ sputtered seed layers allows the deposition of CVD Al on SiO/sub 2/ without having to expose the wafers to TiCl/sub 4/, which may leave Cl residue and cause corrosion. In addition, the CVD films deposited on a TiN seed layer demonstrate smooth morphology and high conductivity and show no presence of the pinholes or interfacial voids which rendered earlier CVD Al films unusable for VLSI. The TIBA process is done at low temperature of 250 degrees C, and TiN is an accepted barrier metal. The combined TiN/CVD Al process promises a low-cost, high-quality manufacturable process for VLSI metallization.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125052156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An optimized high pressure tungsten process for VLSI interconnect and plug applications 为VLSI互连和插头应用优化的高压钨制程
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127885
M. Shenasa, T. Davies
{"title":"An optimized high pressure tungsten process for VLSI interconnect and plug applications","authors":"M. Shenasa, T. Davies","doi":"10.1109/VMIC.1990.127885","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127885","url":null,"abstract":"A manufacturable blanket CVD-W process developed to satisfy the fill properties required for plug formation, as well as the bulk resistivity and reflectivity properties needed in order to use tungsten as first metal, is described. The optimized process provides low contact resistivity to both doped polycrystalline silicon and silicides. A discussion is presented of effects of process parameters (namely temperature, gas ratios, and flow rates) for a chemical vapor deposition of tungsten on the resultant film properties and contact resistance. It is shown that deposition temperature has the greatest effect. An inverse relationship is noted between contact resistance and temperature.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123417118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Electron cyclotron resonance (ECR) deposited SiO/sub 2/ films for interlayer dielectric application 电子回旋共振(ECR)沉积SiO/ sub2 /薄膜的层间介质应用
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127905
C. Chiang, D. Fraser, D. Denison
{"title":"Electron cyclotron resonance (ECR) deposited SiO/sub 2/ films for interlayer dielectric application","authors":"C. Chiang, D. Fraser, D. Denison","doi":"10.1109/VMIC.1990.127905","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127905","url":null,"abstract":"Summary form only given. A study of ECR-CVD oxide for interlayer dielectric deposition is reported. Films have been characterized by various techniques such as stress, Fourier transform infrared (FTIR), etch rate, refractive index, breakdown field, and dielectric constant. The film properties and some process integration issues are discussed. C-V and I-V characteristics of an ECR-CVD deposited oxide indicate an 11-MV/cm breakdown field and 4.0 dielectric constant. Stress vs. temperature curves are shown for films deposited with substrate RF bias and without bias. A planar oxide surface on both a high-aspect-ratio gap and a contact topography is shown. As the RF bias increases, the deposition rate decreases, the Si-O peak width narrows, the film stress reduces, and the wet etch rate reduces. The threshold voltage shift caused by UV radiation when microwave power increases is shown.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128741740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sequential sputter deposition of titanium nitride and aluminum 氮化钛和铝的顺序溅射沉积
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127890
H. Giboa, R. Mosely, H. Talieh, X. S. Guo
{"title":"Sequential sputter deposition of titanium nitride and aluminum","authors":"H. Giboa, R. Mosely, H. Talieh, X. S. Guo","doi":"10.1109/VMIC.1990.127890","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127890","url":null,"abstract":"A sequential deposition process (without air exposure or postdeposition anneal) in a multichamber UHV magnetron sputter deposition system is described. The TiN film has low resistivity (40 mu Omega -cm), low stress (0.23*10/sup 9/ dyne/cm/sup 2/), and excellent diffusion barrier properties; it is stable after a 600 degrees C, 30-min anneal. For nonoptimum films, a RF bias is shown to enhance the TiN barrier property. Oxygen addition during deposition increases film resistivity. Air exposure forms a titanium oxide layer in the Al-TiN interface, reducing the diffusion of titanium from TiN into aluminum.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"207 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127323246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel zero-overlap/enclosure metal interconnection technology for high density logic VLSIs 一种用于高密度逻辑vlsi的新型零重叠/封闭金属互连技术
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127837
H. Shibata, N. Ikeda, M. Nagamatsu, Y. Asahi, K. Maeguchi
{"title":"A novel zero-overlap/enclosure metal interconnection technology for high density logic VLSIs","authors":"H. Shibata, N. Ikeda, M. Nagamatsu, Y. Asahi, K. Maeguchi","doi":"10.1109/VMIC.1990.127837","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127837","url":null,"abstract":"A novel metal interconnection structure with self-defined metal overlap/enclosure of contact/via-hole technology utilizing polysilicon side-wall spacers and plug (SEMOCS) is proposed. It can realize a drastic reduction of metal pitch for high-density logic VLSIs. In addition, by applying a selective CVD-W technique to the via-hole filling, zero metal overlap of the via was also achieved. To verify the advantages of the technology, it was applied to a 32-b CMOS multiplier with triple-level metal interconnections. The chip area was reduced and higher-speed multiplication was achieved due to the reduction of parasitic capacitance resulting from the shrinkage of diffusion area and metal length.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126663763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Numerical simulation of CVD trench filling using a surface reaction coefficient model 基于表面反应系数模型的CVD沟槽充填数值模拟
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127919
J. Rey, L. Cheng, J. Mcvittie, K. Saraswat
{"title":"Numerical simulation of CVD trench filling using a surface reaction coefficient model","authors":"J. Rey, L. Cheng, J. Mcvittie, K. Saraswat","doi":"10.1109/VMIC.1990.127919","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127919","url":null,"abstract":"A simulator has been developed to predict the surface evolution during deposition of different structures. This simulator is part of the Stanford Profile Emulator for Etching and Deposition in IC Engineering (SPEEDIE). Recently, it has been shown by L.Y. Cheng et al. (1989) that low-pressure chemical vapor deposition (LPCVD) of SiO/sub 2/ can be characterized by a single surface reaction coefficient determined by the source gases and processing conditions. Experimental and simulation results of LPCVD SiO/sub 2/ trench filling from two different sources (silane and DES) are presented. The utility of this type of simulation is illustrated through plots of trench design to be completely filled in CVD processes.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"56 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131872448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书