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Seventh International IEEE Conference on VLSI Multilevel Interconnection最新文献

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A low-temperature in-situ deposition and planarizing phosphosilicate glass process for filling high-aspect-ratio topography 一种用于高纵横比地形图填充的低温原位沉积和平面化磷硅酸盐玻璃工艺
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127846
S. Pennington, D. Hallock
{"title":"A low-temperature in-situ deposition and planarizing phosphosilicate glass process for filling high-aspect-ratio topography","authors":"S. Pennington, D. Hallock","doi":"10.1109/VMIC.1990.127846","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127846","url":null,"abstract":"A low-temperature (i.e. 400 degrees C) phosphosilicate glass (PSG) passivation process has been developed that will fill high-aspect-ratio (i.e. 3:1) topography and that can be planarized in situ without a high-temperature (i.e. 800-1100 degrees C) reflow anneal. A tetraethylorthosilicate (TEOS)/ozone chemical vapor deposition (CVD) process, with triethylphosphine (TEP) as the dopant, deposits the PSG. CVD boron oxide (B/sub 2/O/sub 3/) reflows as it is deposited and is used as a sacrificial planarization material. In addition to the high-aspect-ratio fill and in-situ planarization, the PSG process is run as an integrated sequence on a single tool, which optimizes process time and control.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127635744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Feasibility of a novel modular approach for planarization of a submicron triple-level metal CMOS process 一种新型模组化亚微米三层金属CMOS工艺的可行性
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127928
N. Parekh, A. Butler, W. Doedel, W. Heesters, L. Forester
{"title":"Feasibility of a novel modular approach for planarization of a submicron triple-level metal CMOS process","authors":"N. Parekh, A. Butler, W. Doedel, W. Heesters, L. Forester","doi":"10.1109/VMIC.1990.127928","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127928","url":null,"abstract":"The feasibility of a triple-level-metal submicron CMOS process using proven and manufacturable modules is demonstrated. While resist etchback and a silicate SOG (spin-on glass) sandwich are used for planarization at the polysilicon and first metal, respectively, neither of these process modules is feasible for the second-metal planarization due to the severe aspect ratios at this stage of the process. With resist etchback, voiding occurred in the deposited PECVD (plasma-enhanced chemical vapor deposition) layer prior to etchback, while with silicate SOG severe cracking was observed. Both these problems were resolved with a combined process where a thin SOG layer was used to prevent void formation in the subsequent PECVD layer, and the resist etchback scheme was then used to fully planarize prior to the third-metal deposition. Excellent planarity was obtained with <5% resistance differences measured on third metal running over and without topography. While reliability aspects have not yet been evaluated, it is not expected to be an issue based on previous experience with both silicate SOG and resist etchback planarization.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115929537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization of multiple coupled interconnection lines from time domain measurement 多耦合互连线时域测量特性研究
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127917
V. K. Tripathi, J. B. Rettig, L. Hayden
{"title":"Characterization of multiple coupled interconnection lines from time domain measurement","authors":"V. K. Tripathi, J. B. Rettig, L. Hayden","doi":"10.1109/VMIC.1990.127917","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127917","url":null,"abstract":"Measurement techniques used to characterize the uniformly and nonuniformly coupled interconnects in high-speed single-layered and multilayered structures are reported. For an N-line structure, time-domain reflectometer (TDR) measurements can be used to extract all the normal mode parameters of the coupled interconnect system. These include N*(N+1)/2 independent characteristic impedance matrix elements, N eigenvalues representing the normal mode velocities, and a voltage or current eigenvector matrix. The basic excitation response model is shown. For uniformly coupled lines N sets of linearly independent measurements can be made where step waveforms are applied at specified nodes and the response is measured at all the nodes. With a multichannel TDR system it is possible to excite more than one line at a time, e.g. the common and differential modes of a pair of coupled lines. The characteristic impedance matrix elements are evaluated in terms of the generalized reflection coefficient or the scattering matrix elements at the input end in terms of N linearly independent excitations.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124300093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An investigation of device instabilities arising from the encapsulation material and composition 由封装材料和组成引起的器件不稳定性的研究
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127895
J. Gasner, A. Ito, R. Nowak
{"title":"An investigation of device instabilities arising from the encapsulation material and composition","authors":"J. Gasner, A. Ito, R. Nowak","doi":"10.1109/VMIC.1990.127895","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127895","url":null,"abstract":"Two factorial experiments were designed to identify process variables and material compositions for improving hot-carrier-induced MOSFET device instability. The first experiment was designed to identify what factors related to the passivation process are most important. The second experiment concentrated on the composition and thickness of the double-layer nitride-oxide passivation. The results indicate that improvement is achieved by adding an oxide layer under the plasma silicon nitride and performing a sinter prior to the nitride deposition rather than afterwards. The most significant factors were the nitride composition, the thickness of the oxide layer, and the sinter atmosphere.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"211 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115895367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A thermally stable salicide process using N/sub 2/ implantation into TiSi/sub 2/ N/sub - 2/注入TiSi/sub - 2/的热稳定水化工艺
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127882
A. Nishiyama, Y. Akasaka, Y. Ushiku, K. Hishioka, Y. Suizu, M. Shiozaki
{"title":"A thermally stable salicide process using N/sub 2/ implantation into TiSi/sub 2/","authors":"A. Nishiyama, Y. Akasaka, Y. Ushiku, K. Hishioka, Y. Suizu, M. Shiozaki","doi":"10.1109/VMIC.1990.127882","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127882","url":null,"abstract":"TiSi/sub 2/ is an appropriate candidate for the self-aligned silicide (salicide) process. However, it degrades morphologically and the film sheet resistance increases during high-temperature annealing. A thermally stable salicide process using N/sub 2/ implantation into TiSi/sub 2/ has been developed in order to retard this phenomenon. The morphology of the TiSi/sub 2/ film and the film sheet resistance were evaluated as a function of implanted N/sub 2/ dose after high-temperature annealing. The sample which received the highest dose exhibited the best film morphology, while there is an optimum dose for maintaining the film sheet resistance at its maximum value. The dependence of sheet resistance on implanted N/sub 2/ dose is discussed in terms of agglomeration, film composition, and implantation damage. A successful application to a submicron MOS transistor is presented.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123247628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A new etching process of aluminum alloy for submicron multi-level metallization 一种用于亚微米多层金属化的铝合金蚀刻新工艺
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127877
S. Dohmae, S. Mayumi, S. Ueda
{"title":"A new etching process of aluminum alloy for submicron multi-level metallization","authors":"S. Dohmae, S. Mayumi, S. Ueda","doi":"10.1109/VMIC.1990.127877","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127877","url":null,"abstract":"A new dry etch process for Al alloy films where the fluorinated polymer films are formed on metal sidewalls by plasma treatment with CHF/sub 3/ between main etch and overetch was developed. Reentrance in profile and critical dimension (CD) losses are completely suppressed by this process. The yields of submicron metal patterns fabricated by this process are much higher with a larger process window than by a conventional process. The results of the Auger electron spectroscopy (AES) analyses on the sidewall reveal that the fluorinated polymer films are durable enough to prevent side etching and after-corrosion of Al-Si-Cu interconnects.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125182926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of contact hole filling and multilevel metallization on gate oxide integrity and transistor performance 接触孔填充和多层金属化对栅极氧化物完整性和晶体管性能的影响
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127853
U. Schwalke, G. Roska
{"title":"Effects of contact hole filling and multilevel metallization on gate oxide integrity and transistor performance","authors":"U. Schwalke, G. Roska","doi":"10.1109/VMIC.1990.127853","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127853","url":null,"abstract":"Effects of tungsten and polysilicon contact hole fillings as well as multilevel metallization on gate oxide integrity and transistor performance are evaluated. The data indicate that back-end processing may deteriorate gate oxide quality and hence degrade transistor performance. Monitoring gate oxide damage as a function of metallization process steps revealed severe oxide damage which is mainly generated by reactive ion etching and metal sputtering. However, subsequent processing at elevated temperatures (e.g. oxide or polysilicon deposition) efficiently reduced gate oxide damage prior to the final forming gas anneal. In the case of polysilicon contact hole filling this results in extremely low interface trap densities on fully processed wafers and excellent device characteristics. In contrast, severe degradation of transistor performance was found in the case of tungsten contact hole filling.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126542708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization and simulation of PECVD and APCVD oxide step coverage PECVD和APCVD氧化台阶覆盖的表征与模拟
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127860
P. Lesaicherre, A. Gérodolle, P. Brouquet, N. Rossiter
{"title":"Characterization and simulation of PECVD and APCVD oxide step coverage","authors":"P. Lesaicherre, A. Gérodolle, P. Brouquet, N. Rossiter","doi":"10.1109/VMIC.1990.127860","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127860","url":null,"abstract":"The step coverage of plasma-enhanced chemical vapor deposition (PECVD) and atmospheric-pressure CVD (APCVD) glass films has been studied experimentally and by computer simulation. An original method is proposed to characterize the step coverage of a deposition process. Based on the graphic representation of step coverage results on dimensionless diagrams, this method allows comparison of deposition techniques, as well as the quantification of the influence on step coverage of several parameters (step slope, underlying step material). Application of the method to the global evaluation of PECVD models is presented on two examples. The hemispherical model of the process simulator SAMPLE is not suited to the simulation of PECVD, whereas the TITAN 5 model leads to a good agreement with the experimental results. A predictive tool is thus obtained, which allows optimization of planarization processes by computer simulation.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129191134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Time resolved reflectivity measurements of Al alloys during excimer laser planarization 准分子激光平面化过程中铝合金的时间分辨反射率测量
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127848
B. Woratschek, P. Carey, F. Bachmann
{"title":"Time resolved reflectivity measurements of Al alloys during excimer laser planarization","authors":"B. Woratschek, P. Carey, F. Bachmann","doi":"10.1109/VMIC.1990.127848","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127848","url":null,"abstract":"Time-resolved reflectivity measurements have been made in situ during XeCl ( lambda =308 nm) excimer laser planarization of Al, AlSi(1%), and AlSi(1%)Cu(0.5%) at 25, 250, and 400 degrees C. The reflectivity change observed when using a HeNe ( lambda =632.8 nm) probe beam is assumed to indicate layer melting. Metal melt times have been determined as a function of laser energy fluence, substrate temperature, and oxide thickness. The results show that metal melt times increase with laser energy fluence and substrate temperature, the pure Al melts for shorter times and needs higher laser energy fluences than the corresponding alloys, and little difference is seen in the melting characteristics of the alloys. The best conditions for insuring complete planarization (long melt times) would thus be for conditions in which the wafer is heated.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134312102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Sticking coefficient as a single parameter to characterize step coverage of SiO/sub 2/ processes 粘附系数作为表征SiO/ sub2 /工艺步骤覆盖的单一参数
Seventh International IEEE Conference on VLSI Multilevel Interconnection Pub Date : 1990-06-12 DOI: 10.1109/VMIC.1990.127913
L. Cheng, J. Rey, J. Mcvittie, K. Saraswat
{"title":"Sticking coefficient as a single parameter to characterize step coverage of SiO/sub 2/ processes","authors":"L. Cheng, J. Rey, J. Mcvittie, K. Saraswat","doi":"10.1109/VMIC.1990.127913","DOIUrl":"https://doi.org/10.1109/VMIC.1990.127913","url":null,"abstract":"The authors use a single parameter, the sticking coefficient (or reaction probability), to model the step coverage of low pressure chemical vapor deposited (LPCVD) SiO/sub 2/ films. Earlier studies show that a low sticking coefficient, instead of surface diffusion, is the key step coverage improving mechanism. A simulation program based on a hypothesized reaction mechanism has been written to simulate deposition profiles. The program is capable of simulating redeposition and surface diffusion. Simulated profiles, using a single sticking coefficient (SC), agree well with experimental oxide films deposited on a variety of different geometries. The coefficient depends strongly on the silicon source used, and its magnitude decreases with increasing temperature.<<ETX>>","PeriodicalId":320318,"journal":{"name":"Seventh International IEEE Conference on VLSI Multilevel Interconnection","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124031036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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