A novel zero-overlap/enclosure metal interconnection technology for high density logic VLSIs

Abstract

A novel metal interconnection structure with self-defined metal overlap/enclosure of contact/via-hole technology utilizing polysilicon side-wall spacers and plug (SEMOCS) is proposed. It can realize a drastic reduction of metal pitch for high-density logic VLSIs. In addition, by applying a selective CVD-W technique to the via-hole filling, zero metal overlap of the via was also achieved. To verify the advantages of the technology, it was applied to a 32-b CMOS multiplier with triple-level metal interconnections. The chip area was reduced and higher-speed multiplication was achieved due to the reduction of parasitic capacitance resulting from the shrinkage of diffusion area and metal length.<>