Characterization of mechanical planarization processes

Abstract

A square-wave test structure is described which provides a useful vehicle for characterizing planarization processes. The structure is designed for easy replication in different laboratories to allow comparison of planarization methods in spite of their inherent pattern sensitivity. Results obtained for a number of mechanical planarization processes on this structure are presented. A planarization rate parameter p is defined and used to describe the planarization of features in the width range of 1-10 mm, a range which is important because of the effects of long-range pattern density variations in VLSI chips. Polishing pad structure and condition are found to be the most important determiners of p, and results for several commercially available pads are reported. Mechanical planarization adequate to handle the interlayer dielectric (ILD) planarization requirements of most chips is demonstrated.<>