2019 IEEE 13th International Conference on ASIC (ASICON)最新文献_第7页

Hardware Implementation of Convolutional Neural Network for Face Feature Extraction 卷积神经网络人脸特征提取的硬件实现

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983575

Ru Ding, Xuemei Tian, Guoqiang Bai, G. Su, Xingjun Wu

{"title":"Hardware Implementation of Convolutional Neural Network for Face Feature Extraction","authors":"Ru Ding, Xuemei Tian, Guoqiang Bai, G. Su, Xingjun Wu","doi":"10.1109/ASICON47005.2019.8983575","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983575","url":null,"abstract":"As an important feed-forward neural network in the field of deep learning, convolutional neural network (CNN) has been widely used in image classification, face recognition, natural language processing and document analysis in recent years. CNN has a large amount of data and many multiply and accumulate (MAC) operations. With the diversity of application files, the channel sizes and kernel sizes of CNN are diverse, while the existing hardware platform mostly adopts the average optimization technology, which causes the waste of computing resources. In this paper, a special configurable convolution computing array is designed, which contains 15 convolution units, each PE contains 6×6 MAC operations, it can be configured to calculate three different kernel sizes of 5×5, 3×3 and 1×1. At the same time, pipeline structure is used to synchronize convolution and pooling operations, which reduces the storage of intermediate results. We design the special hardware structure to optimize DeepID network. Tested on Altera Cyclone V FPGA, the peak performance of each convolution layer at 50 MHz is 27 GOPS, and the average utilization of the MAC is 92%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132676008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Performance optimization for LDO regulator based on the differential evolution 基于差分进化的LDO调节器性能优化

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983642

Jintao Li, Yanhan Zeng, Hailong Wu, R. Li, Jun Zhang, Hongzhou Tan

引用次数: 2

Scalable Modeling for the CPW Gap Discontinuity at Frequency up to 150 GHz 频率高达150 GHz的CPW间隙不连续的可扩展建模

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983616

Hao Sun, Jun Fu, Wenpu Cui, Tianling Ren, Linlin Liu, Wei Zhou, Quan Wang, Ao Guo

引用次数: 0

A Low-delay Configurable Register for FPGA FPGA低延迟可配置寄存器

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983553

Zhiyin Lu, Jiafeng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jinmei Lai, Jian Wang

引用次数: 2

An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency 一种适用于2.2 MHz频率开关电源的超低功耗逐周期限流器

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983457

Yue Shi, Jiawen Wang, Jianwen Cao, Ze-kun Zhou

{"title":"An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency","authors":"Yue Shi, Jiawen Wang, Jianwen Cao, Ze-kun Zhou","doi":"10.1109/ASICON47005.2019.8983457","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983457","url":null,"abstract":"A high performance, low power cycle-by-cycle current limiter is proposed in this paper, which can prevent switching-mode power supply from damage under over current or short circuit conditions. With the clamping effect formed by feedback loop with operational amplifier, the output current can be proportionally sampled and transferred to a voltage relative to ground. In order to further reduce power consumption, the sampling loop with low bias current is only enabled during the on time of high-side transistors. Besides, an assistant clamping circuit is presented to accelerate the settling time of every cycle for high-speed applications. What's more, a source-input comparator with voltage clamper is adopted to judge the status of output current, which can realize reference level and comparison at the same time for further speed improvement with lower power requirement. The proposed current limiter is implemented in a standard 0.18µm CMOS process, whose verification results within a 3A, 2.2MHz Buck converter show that a 39ns response time with 8.6MHz bandwidth is realized with only 2µA on-state and zero off-state current consumption.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115612315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-speed Classification of AER Data Based on a Low-cost Hardware System 基于低成本硬件系统的AER数据高速分类

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983433

J. Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, N. Wu, Gang Luo

引用次数: 1

Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor 在可重构对称密码处理器上提高椭圆曲线密码算法能量效率的方法

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983539

Zhao Tuo, Tao Chen, Wei Li, Danyang Yang

引用次数: 0

Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters 双轴应变GeOI衬底单轴拉伸应力Ge n- finfet的性能研究及其对Ge CMOS逆变器的影响

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/asicon47005.2019.8983454

R. Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao

引用次数: 0

A Simple Steady Timing Resilient Sample Based on Delay Data Sense Detection 基于延迟数据感知检测的简单稳定定时弹性采样

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983641

Xuemei Fan, Rujin Wang, Qinghui Zeng, Hao Liu, Shengli Lu

引用次数: 1

A radiation resistant library based on DICE and fault-tolerant delay filtering techniques in CMOS 0.18μm technology 基于CMOS 0.18μm技术的DICE和容错延迟滤波技术的抗辐射库

2019 IEEE 13th International Conference on ASIC (ASICON) Pub Date : 2019-10-01 DOI: 10.1109/ASICON47005.2019.8983582

Yangsheng Wang, Yanyan Gao, Chong Feng, N. Zhang

引用次数: 0