A Simple Steady Timing Resilient Sample Based on Delay Data Sense Detection

The performance and reliability of integrated circuits are susceptible to PVTA variations. Conventional designs reserve certain timing margin and consider the worst-case to avoid these side effects. Timing resilient circuits can reduce the timing safe margin with the cost of excessive energy overhead and an unsteady state under a low voltage. In this study, we exploit a simple steady timing resilient sample by expanding previous works to save considerable extra power overhead. This sample executes timing errors detection based on the delay data sense detection and is implemented both on latches and data strobe flip-flops to recover errors with merely four extra transistors. The effectiveness and efficiency are evaluated by the design of a systolic array CNN accelerator in the 40-nm process. Simulation results demonstrate that the accelerator can achieve a stable performance without any accuracy loss, with the voltage scaled to 0.57V.