High-speed Classification of AER Data Based on a Low-cost Hardware System

Abstract

This paper proposes a low-cost hardware system for rapid classification of visual objects encoded in the address-event representation (AER) format. A lightweight statistical inference algorithm is implemented in the proposed hardware to process the asynchronous pixel address streams from an AER visual sensor. The algorithm involves only a few simple operations for patch-based binary feature extraction and Random Ferns inference, which are highly parallelized and accelerated by our dedicated hardware architecture. Simulation results suggested that our hardware system was able to process as many as 50M address events per second and achieved 75% classification accuracy for the popular MNIST-DVS dataset. Compared to other AER classification systems, our low-cost FPGA implementation is more plausible for embedded applications because of its similar accuracy and higher system throughput.