16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)最新文献_第9页

Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs 基于时间-功率-温度依赖性的三维集成电路热规划的反思

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722195

Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, J. Cong

{"title":"Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs","authors":"Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, J. Cong","doi":"10.1109/ASPDAC.2011.5722195","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722195","url":null,"abstract":"Due to the increased power density and lower thermal conductivity, 3D is faced with heat dissipation and temperature problem seriously. Previous researches show that leakage power and delay are both relevant to temperature. The timing-power-temperature dependence will potentially negate the performance improvement of 3D designs. TSV (Through-Silicon-Vias) has been shown as an effective way to help heat removal, but they create routing congestions. Therefore, how to reach the trade-off between temperature, via number and delay is required to be solved. Different from previous works on TSV planning which ignored the effects of leakage power, in this paper, we integrate temperature-leakage-timing dependence into thermal via planning of 3D ICs. A weighted via insertion approach, considering both performance and heat dissipation with resource constraint, is proposed to achieve the best balance among delay, via number and temperature. Experiment results show that, with leakage power and resource constraint considered the temperature and via number required can be quite different, and weighted TSV insertion approach can improve thermal via number, by about 5.6%.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

A fully integrated shock wave transmitter with an on-chip dipole antenna for pulse beam-formability in 0.18-μm CMOS 具有片上偶极子天线的完全集成的冲击波发射器，用于0.18 μm CMOS的脉冲波束成形性

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722161

N. Khanh, M. Sasaki, K. Asada

引用次数: 5

On the impact of gate oxide degradation on SRAM dynamic and static write-ability 栅极氧化物降解对SRAM动态和静态可写性的影响

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722278

V. Chandra, R. Aitken

{"title":"On the impact of gate oxide degradation on SRAM dynamic and static write-ability","authors":"V. Chandra, R. Aitken","doi":"10.1109/ASPDAC.2011.5722278","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722278","url":null,"abstract":"Low voltage operation of SRAM arrays is critical in reducing the power consumption of embedded microprocessors. The minimum voltage of operation, Vmin, can be limited by any combination of write failure, read disturb failure, access failure and/or retention failure. Of these, the write failure is often observed as the major Vmin limiter in sub-50nm processes. In addition, the current generation transistors have high-k metal gate (HKMG) and these are prone to degradation due to higher level of electric field stress. The degradation increases Vmin due to increase in dynamic write failures and eventually, static write failures as the supply voltage decreases. We show that there exists a critical breakdown resistance (Rcrit) for a given supply voltage at which the SRAM write failure transitions from being dynamically limited to statically limited. For a 32nm low-power SRAM, the value of Rcrit increases by ∼9X as the supply voltage reduces from 1V to 0.7V. Further, we show that the commonly used SRAM write-assist (WA) techniques do not lower Rcrit and can only improve the write-ability when the breakdown resistance, Rsbd, is larger than Rcrit.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131268091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems 基于片上网络的多核系统中顺序和弱内存一致性模型的实现及性能比较

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722176

Abdul Naeem, Xiaowen Chen, Zhonghai Lu, A. Jantsch

引用次数: 9

Accounting for inherent circuit resilience and process variations in analyzing gate oxide reliability 在栅极氧化物可靠性分析中考虑电路固有弹性和工艺变化

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722275

Jian-wei Fang, S. Sapatnekar

引用次数: 8

Cut-demand based routing resource allocation and consolidation for routability enhancement 基于减少需求的路由资源分配和可达性增强的整合

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722247

Fong-Yuan Chang, Sheng-Hsiung Chen, R. Tsay, Wai-Kei Mak

引用次数: 5

SETmap: A soft error tolerant mapping algorithm for FPGA designs with low power SETmap:一种用于FPGA低功耗设计的软容错映射算法

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722219

Chi-Chen Peng, Chen Dong, Deming Chen

引用次数: 3

Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC 用于移动SoC和3D-IC的嵌入式存储器和电阻性RAM (RRAM)的电路设计挑战

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722184

Meng-Fan Chang, P. Chiu, S. Sheu

引用次数: 23

Throughput optimization for latency-insensitive system with minimal queue insertion 最小队列插入下延迟不敏感系统的吞吐量优化

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722257

Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho

{"title":"Throughput optimization for latency-insensitive system with minimal queue insertion","authors":"Juinn-Dar Huang, Yi-Hang Chen, Ya-Chien Ho","doi":"10.1109/ASPDAC.2011.5722257","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722257","url":null,"abstract":"As fabrication process exploits even deeper submicron technology, global interconnect delay is becoming one of the most critical performance obstacles in system-on-chip (SoC) designs nowadays. Recent years latency-insensitive system (LIS), which enables multicycle communication to tolerate variant interconnect delay without substantially modifying pre-designed IP cores, has been proposed to conquer this issue. However, imbalanced interconnect latency and communication back-pressure residing in an LIS still degrade system throughput. In this paper, we present a throughput optimization technique with minimal queue insertion. We first model a given LIS as a quantitative graph (QG), which can be further compacted using the proposed techniques, so that much bigger problems can be handled. On top of QG, the optimal solution with minimal queue size can be achieved through integer linear programming based on the proposed constraint formulation in an acceptable runtime. The experimental results show that our approach can deal with moderately large systems in a reasonable runtime and save about 28% of queues compared to the prior art.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"76 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120923062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An RTL-to-GDS2 design methodology for advanced system LSI 高级系统LSI的RTL-to-GDS2设计方法

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.5555/1950815.1950962

N. Nishiguchi

引用次数: 0