16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)最新文献_第8页

A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles 一种65nm触发器阵列，用于测量对高能中子和α粒子的软错误弹性

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722306

J. Furuta, C. Hamanaka, Kazutoshi Kobayashi, H. Onodera

引用次数: 8

Analog circuit verification by statistical model checking 模拟电路通过统计模型检查验证

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722168

Ying-Chih Wang, Anvesh Komuravelli, P. Zuliani, E. Clarke

引用次数: 16

Register pressure aware scheduling for high level synthesis 登记压力感知调度高层次合成

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722234

Rami Beidas, W. Mong, Jianwen Zhu

{"title":"Register pressure aware scheduling for high level synthesis","authors":"Rami Beidas, W. Mong, Jianwen Zhu","doi":"10.1109/ASPDAC.2011.5722234","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722234","url":null,"abstract":"Variations of list scheduling became the de-facto standard of scheduling straight line code in software compilers, a trend faithfully inherited by high-level synthesis solutions. Due to its nature, list scheduling is oblivious of the tightly coupled register pressure; a dangling fundamental problem that has been attacked by the compiler community for decades, and which results, in case of highlevel synthesis, in excessive instantiations of registers and accompanying steering logic. To alleviate this problem, we propose a synthesis framework called soft scheduling, which acts as a resource unconstrained pre-scheduling stage that restricts subsequent scheduling to minimize register pressure. This optimization objective is formulated as a live range minimization problem, a measure shown to be proportional to register pressure, and optimally solved in polynomial time using minimum cost network flow formulation. Unlike past solutions in the compiler community, which try to reduce register pressure by local serialization of subject instructions, the proposed solution operates on the entire basic block or hyperblock and systematically handles instruction chaining subject to the same objective. The application of the proposed solution to a set of real-life benchmarks results in a register pressure reduction ranging, on average, between 11% and 41% depending on the compilation and synthesis configurations with minor 2% to 4% increase in schedule latency.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"25 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114132540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Simultaneous redundant via insertion and line end extension for yield optimization 同时冗余通过插入和线端延伸为良率优化

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722266

Shing-Tung Lin, Kuang‐Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao

引用次数: 14

Vertical interconnects squeezing in symmetric 3D mesh Network-on-Chip 垂直互连挤压对称三维网格片上网络

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722213

Cheng Liu, Lei Zhang, Yinhe Han, Xiaowei Li

引用次数: 58

A self-testing and calibration method for embedded successive approximation register ADC 一种嵌入式逐次逼近寄存器ADC的自测试和校准方法

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722279

Xuan-Lun Huang, Ping-Ying Kang, Hsiu-Ming Chang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, D. Kwai, Cheng-Wen Wu

引用次数: 13

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits CELONCEL:针对高性能集成电路的三维单片集成的有效设计技术

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722210

Shashikanth Bobba, A. Chakraborty, O. Thomas, P. Batude, T. Ernst, O. Faynot, D. Pan, G. Micheli

{"title":"CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits","authors":"Shashikanth Bobba, A. Chakraborty, O. Thomas, P. Batude, T. Ernst, O. Faynot, D. Pan, G. Micheli","doi":"10.1109/ASPDAC.2011.5722210","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722210","url":null,"abstract":"3-D monolithic integration (3DMI), also termed as sequential integration, is a potential technology for future gigascale circuits. Since the device layers are processed in sequential order, the size of the vertical contacts is similar to traditional contacts unlike in the case of parallel 3-D integration with through silicon vias (TSVs). Given the advantage of such small contacts, 3DMI enables manufacturing multiple active layers very close to each other. In this work we propose two different strategies of stacking standard cells in 3-D without breaking the regularity of the conventional design flow: a) Vertical stacking of diffusion areas (Intra-Cell stacking) that supports complete reuse of 2-D physical design tools and b) vertical stacking of cells over others (Cell-on-Cell stacking). A placement tool (CELONCEL-placer) targeting the Cell-on-Cell placement problem is proposed to allow high quality 3-D layout generation. Our experiments demonstrate the effectiveness of CELONCEL technique, fetching us an area gain of 37.5%, 15.51% reduction in wirelength, and 13.49% improvement in overall delay, compared with a 2-D case when benchmarked across an interconnect dominated low-density-parity-check (LDPC) decoder at 45nm technology node.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115499595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 66

Power management strategies in data transmission 数据传输中的电源管理策略

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722271

Tiefei Zhang, Ying-Jheng Chen, Che-Wei Chang, Chuan-Yue Yang, Tei-Wei Kuo, Tianzhou Chen

引用次数: 3

Leakage conscious DVS scheduling for peak temperature minimization 泄漏意识分布式交换机调度峰值温度最小化

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722173

Vivek Chaturvedi, Gang Quan

引用次数: 17

Robust spatial correlation extraction with limited sample via L1-norm penalty 基于l1范数惩罚的有限样本鲁棒空间相关提取

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722273

M. Gao, Zuochang Ye, Dajie Zeng, Yan Wang, Zhiping Yu

引用次数: 1