16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)最新文献_第10页

Run-time adaptive performance compensation using on-chip sensors 使用片上传感器的运行时自适应性能补偿

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722199

M. Hashimoto

引用次数: 2

An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits 一种有效的混合引擎，用于运算电路的范围分析和整数位宽分配

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722233

Yu Pang, K. Radecka, Z. Zilic

引用次数: 22

Variation-aware logic mapping for crossbar nano-architectures 交叉杆纳米结构的变化感知逻辑映射

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722207

M. Zamani, M. Tahoori

引用次数: 15

Robust power gating reactivation by dynamic wakeup sequence throttling 动态唤醒序列节流的鲁棒功率门控再激活

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722263

Tung-Yeh Wu, Shih-Hsin Hu, J. Abraham

引用次数: 0

Area-efficient FPGA logic elements: Architecture and synthesis 面积高效的FPGA逻辑元件:架构与合成

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722215

J. Anderson, Qiang Wang

{"title":"Area-efficient FPGA logic elements: Architecture and synthesis","authors":"J. Anderson, Qiang Wang","doi":"10.1109/ASPDAC.2011.5722215","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722215","url":null,"abstract":"We consider architecture and synthesis techniques for FPGA logic elements (function generators) and show that the LUT-based logic elements in modern commercial FPGAs are over-engineered. Circuits mapped into traditional LUT-based logic elements have speeds that can be achieved by alternative logic elements that consume considerably less silicon area. We introduce the concept of a trimming input to a logic function, which is an input to a K-variable function about which Shannon decomposition produces a cofactor having fewer than K −1 variables. We show that trimming inputs occur frequently in circuits and we propose low-cost asymmetric FPGA logic element architectures that leverage the trimming input concept, as well as some other properties of a circuit's AND-inverter graph (AIG) functional representation. We describe synthesis techniques for the proposed architectures that combine a standard cut-based FPGA technology mapping algorithm with two straightforward procedures: 1) Shannon decomposition, and 2) finding non-inverting paths in the circuit's AIG. The proposed architectures exhibit improved logic density versus traditional LUT-based architectures with minimal impact on circuit speed.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114482485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 49

Exploration of VLSI CAD researches for early design rule evaluation VLSI CAD研究在早期设计规则评估中的探索

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722223

Chul-Hong Park, D. Pan, K. Lucas

引用次数: 3

All-out fight against yield losses by design-manufacturing collaboration in nano-lithography era 纳米光刻时代设计制造协同对抗良率损失

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722220

S. Inoue, S. Kobayashi

引用次数: 0

An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation 超低电压LC-VCO，具有频率扩展电路，可用于未来的0.5 v时钟生成

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722159

W. Deng, K. Okada, A. Matsuzawa

引用次数: 2

Low power discrete voltage assignment under clock skew scheduling 时钟倾斜调度下的低功耗离散电压分配

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722244

Li Li, Jian Sun, Yinghai Lu, H. Zhou, Xuan Zeng

{"title":"Low power discrete voltage assignment under clock skew scheduling","authors":"Li Li, Jian Sun, Yinghai Lu, H. Zhou, Xuan Zeng","doi":"10.1109/ASPDAC.2011.5722244","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722244","url":null,"abstract":"Multiple Supply Voltage (MSV) assignment has emerged as an appealing technique in low power IC design, due to its flexibility in balancing power and performance. However, clock skew scheduling, which has great impact on criticality of combinational paths in sequential circuit, has not been explored in the merit of MSV assignment. In this paper, we propose a discrete voltage assignment algorithm for sequential circuit under clock scheduling. The sequential MSV assignment problem is first formulated as a convex cost dual network flow problem, which can be optimally solved in polynomial time assuming delay of each gate can be chosen in continuous domain. Then a mincut-based heuristic is designed to convert the unfeasible continuous solution into feasible discrete solution while largely preserving the global optimality. Besides, we revisit the hardness of the general discrete voltage assignment problem and point out some misunderstandings on the approximability of this problem in previous related work. Benchmark test for our algorithm shows 9.2% reduction in power consumption on average, in compared with combinational MSV assignment. Referring to the continuous solution obtained from network flow as the lower bound, the gap between our solution and the lower bound is only 1.77%.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132221995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults NS-FTR:一种容错路由方案，适用于具有永久和运行时间歇故障的片上网络

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) Pub Date : 2011-01-25 DOI: 10.1109/ASPDAC.2011.5722231

S. Pasricha, Yong Zou

{"title":"NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults","authors":"S. Pasricha, Yong Zou","doi":"10.1109/ASPDAC.2011.5722231","DOIUrl":"https://doi.org/10.1109/ASPDAC.2011.5722231","url":null,"abstract":"In sub-65nm CMOS technologies, interconnection networks-on-chip (NoC) will increasingly be susceptible to design time permanent faults and runtime intermittent faults, which can cause system failure. To overcome these faults, NoC routing schemes can be enhanced by adding fault tolerance capabilities, so that they can adapt communication flows to follow fault-free paths. A majority of existing fault tolerant routing algorithms are based on the turn model approach due to its simplicity and inherent freedom from deadlock. However, these turn model based algorithms are either too restrictive in the choice of paths that flits can traverse, or are tailored to work efficiently only on very specific fault distribution patterns. In this paper, we propose a novel fault tolerant routing scheme (NS-FTR) for NoC architectures that combines the North-last and South-last turn models to create a robust hybrid NoC routing scheme. The proposed scheme is shown to have a low implementation overhead and adapt to design time and runtime faults better than existing turn model, stochastic random walk, and dual virtual channel based routing schemes.","PeriodicalId":316253,"journal":{"name":"16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-01-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132530117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 31