Variation-aware logic mapping for crossbar nano-architectures

Abstract

Programmable nano-architectures fabricated based on bottom-up self-assembly process are alternative for CMOS technology to overcome physical barriers as well as increased lithography-based fabrication costs in downscaling. Extreme process variation and high failure rate due to nondeter-ministic self assembly fabrication process pose serious challenges for logic implementation in this technology. In this paper, we analyze the effect of variations on mapped designs and propose an efficient mapping method to reduce variation effects on crossbar nano-architectures. This method takes advantage of reconfigurability and abundance of resources for tolerating variation and improving reliability. The main idea is based on duplicating crossbar input lines as well as swapping rows (columns) of a crossbar to reduce the output dependency and be able to reduce delay variation. Experimental results on a set of benchmarks show that the proposed method can reduce critical path delay up to 74% (57% in average).