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Can beyond-CMOS devices illuminate dark silicon? 超cmos器件能照亮暗硅吗?
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.1145/3230628
Robert Perricone, X. Hu, J. Nahas, M. Niemier
{"title":"Can beyond-CMOS devices illuminate dark silicon?","authors":"Robert Perricone, X. Hu, J. Nahas, M. Niemier","doi":"10.1145/3230628","DOIUrl":"https://doi.org/10.1145/3230628","url":null,"abstract":"Throughout the last decade, the microprocessor industry has been struggling to preserve the benefits of Moore's Law scaling. The persistent scaling of CMOS technology no longer yields exponential performance gains due in part to the growth of dark silicon. With each subsequent technology node generation, power constraints resulting from factors such as sub-threshold leakage currents are projected to further limit the number of transistors that can be simultaneously powered. To overcome the limits of CMOS devices, researchers are working to develop “beyond-CMOS” device technologies. To determine the most promising beyond-CMOS devices, it is necessary to benchmark them against CMOS. In this paper, we present the design and validation of an analytical benchmarking model that evaluates CMOS and beyond-CMOS devices at the architectural-level. Our model is built from the device to the architectural/application-level. Our target architecture is a symmetric multi-core processor executing highly parallel applications (i.e., PARSEC). As a case study, we select one class of promising beyond-CMOS devices, tunneling field-effect transistors, to evaluate against CMOS.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"465 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131166538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A flexible inexact TMR technique for SRAM-based FPGAs 基于sram的fpga灵活的非精确TMR技术
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0631
Shyamsundar Venkataraman, Rui Santos, Akash Kumar
{"title":"A flexible inexact TMR technique for SRAM-based FPGAs","authors":"Shyamsundar Venkataraman, Rui Santos, Akash Kumar","doi":"10.3850/9783981537079_0631","DOIUrl":"https://doi.org/10.3850/9783981537079_0631","url":null,"abstract":"Single Event Upsets (SEUs) inadvertently change the logic memory and thereby the configuration of the Field Programmable Gate Arrays (FPGAs), leading to their incorrect functioning. Traditional methods to tolerate such faults include Triple Modular Redundancy (TMR). However, such method has a high overhead in terms of power and area. Moreover, the inexact methods used in ASICs to overcome this problem are not efficient when applied in FPGAs. Therefore, this paper proposes a novel technique based on heuristic to tolerate faults in SRAM-based FPGAs by using inexact modules in conjunction with TMR, thus reducing the area and power overhead of the design. Experiments run on various MCNC benchmark circuits show the accuracy of the proposed technique. They also show that the design solutions found through this technique only differ 0.52% on average from the optimal ones and savings up to 84.4% in terms of computation time can be reached on average.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127827477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Analog circuit topological feature extraction with unsupervised learning of new sub-structures 基于新子结构无监督学习的模拟电路拓扑特征提取
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0923
Hao Li, Fanshu Jiao, A. Doboli
{"title":"Analog circuit topological feature extraction with unsupervised learning of new sub-structures","authors":"Hao Li, Fanshu Jiao, A. Doboli","doi":"10.3850/9783981537079_0923","DOIUrl":"https://doi.org/10.3850/9783981537079_0923","url":null,"abstract":"This paper presents novel techniques to automatically extract the topological (structural) features in analog circuits. The extracted features include basic building blocks, structural templates and hierarchical structures. Finding structural features is important for tasks like circuit synthesis and sizing, design verification, design reuse, and design knowledge description, summarization and management. The paper presents algorithms for supervised feature extraction and unsupervised learning of new block connections. Experiments discuss feature extraction for a set of 34 state-of-the-art analog circuits.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132760047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs HV/HT汽车智能电源集成电路中少数载流子传播问题的自动诊断
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0291
Yasser Moursy, Hao Zou, R. Iskander, P. Tisserand, D. Ton, G. Pasetti, E. Seebacher, A. Steinmair, T. Gneiting, H. Alius
{"title":"Towards automatic diagnosis of minority carriers propagation problems in HV/HT automotive smart power ICs","authors":"Yasser Moursy, Hao Zou, R. Iskander, P. Tisserand, D. Ton, G. Pasetti, E. Seebacher, A. Steinmair, T. Gneiting, H. Alius","doi":"10.3850/9783981537079_0291","DOIUrl":"https://doi.org/10.3850/9783981537079_0291","url":null,"abstract":"In this paper, a proposed methodology to identify the substrate coupling effects in smart power integrated circuits is presented. This methodology is based on a tool called AUTOMICS to extract substrate parasitic network. This network comprises diodes and resistors that are able to maintain the continuity of minority carrier concentration. The contribution of minority carriers in the substrate noise is significant in high-voltage and high temperature applications. The proposed methodology along with conventional latch-up problem identification for a test case automotive chip AUTOCHIP1 are presented. The time of the proposed methodology is significantly shorter than the conventional one. The proposed methodology could significantly shorten the time-to-market and ameliorate the robustness of the design.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133910065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Decision tree generation for decoding irregular instructions 解码不规则指令的决策树生成
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0066
Katsumi Okuda, Haruhiko Takeyama
{"title":"Decision tree generation for decoding irregular instructions","authors":"Katsumi Okuda, Haruhiko Takeyama","doi":"10.3850/9783981537079_0066","DOIUrl":"https://doi.org/10.3850/9783981537079_0066","url":null,"abstract":"Instruction set simulators (ISS) are indispensable tools for the development of new architectures and embedded software. One essential part of any ISS is its instruction decoder. Since manual implementation of an instruction decoder for a complex instruction set is tedious and error-prone, automatic generation of an instruction decoder is required. However, as a result of the increasing irregularity of instruction encoding because of the incremental addition of instructions, generating efficient instruction decoders is complicated. In this paper, we propose a generation algorithm of a decision tree for decoding irregular instructions. Our algorithm can generate decision trees by using not only significant bits of opcode patterns but also exclusion conditions in decoding entries. Our results on ARMv7, Thumb-2, MIPS64, RH850, and TriCore show that our algorithm generates efficient instruction decoders in terms of both depth and memory consumption regardless of whether the target instruction set is irregular or not.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131914549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications 超低功耗应用的3T-TFET位单元TFET-CMOS混合SRAM设计
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0462
N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, C. Anghel
{"title":"3T-TFET bitcell based TFET-CMOS hybrid SRAM design for Ultra-Low Power applications","authors":"N. Gupta, A. Makosiej, A. Vladimirescu, A. Amara, C. Anghel","doi":"10.3850/9783981537079_0462","DOIUrl":"https://doi.org/10.3850/9783981537079_0462","url":null,"abstract":"This paper presents a TFET/CMOS hybrid SRAM architecture designed to address the requirements for ULP (Ultra-Low Power) applications, like IoT (Internet of Things). A novel 3-Transistor TFET SRAM cell is used for array while CMOS for periphery. The simulation extractions for power and speed are done including wiring and device parasitic capacitance from 4Kb SRAM designed in 28nm FDSOI CMOS process using MOSFETs & Tunnel FETs (TFETs). The proposed 3T-TFET SRAM cell supports aggressive voltage scaling without impacting data stability and allows application of performance boosting techniques without impacting cell leakage. A 0.35 fA/bit memory array leakage current was achieved showing a 14x to 104x improvement compared with state-of-the-art TFET and CMOS SRAM bitcells. Minimum read and write access pulse is evaluated at 1.27ns at sub-1V supply voltage.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134416723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Resource-aware functional ECO patch generation 资源感知功能ECO补丁生成
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0946
An-Che Cheng, I. Jiang, Jing-Yang Jou
{"title":"Resource-aware functional ECO patch generation","authors":"An-Che Cheng, I. Jiang, Jing-Yang Jou","doi":"10.3850/9783981537079_0946","DOIUrl":"https://doi.org/10.3850/9783981537079_0946","url":null,"abstract":"Functional Engineering Change Order (ECO) is necessary for logic rectification at late design stages. Existing works mainly focus on identifying a minimal logic difference between the original netlist and the revised netlist, which is called a patch. The patch is then implemented by technology mapping using spare cells. However, there may be insufficient spare cells around the physical location of the patch, or the wires connecting spare cells are too long, thus causing timing violations and routing congestion. In this paper, we propose a resource-aware functional patch generation approach by gate count and wiring cost estimations. In particular, we estimate the number of spare cells required by a patch and define a cost of wire length on it, which considers the physical location of the patch and a set of nearby spare cells. As a result, the patch with minimal wiring cost instead of minimal size is produced. The experiments are conducted on nine industrial testcases. These testcases reflect real problems faced by designers, and the results show our method is promising.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114541920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits 甲骨文引导的增量SAT解决逆向工程伪装逻辑电路
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0915
Duo Liu, Cunxi Yu, X. Zhang, Daniel E. Holcomb
{"title":"Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits","authors":"Duo Liu, Cunxi Yu, X. Zhang, Daniel E. Holcomb","doi":"10.3850/9783981537079_0915","DOIUrl":"https://doi.org/10.3850/9783981537079_0915","url":null,"abstract":"Layout-level gate camouflaging has attracted interest as a countermeasure against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gates in a circuit are camouflaged, and each camouflaged gate layout can implement a few different logic functions. The security of camouflaging relies on the difficulty of learning the overall combinational logic function without knowing which logic functions the camouflaged gates implement.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114569032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
Resistive configurable associative memory for approximate computing 用于近似计算的电阻式可配置联想存储器
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0454
M. Imani, Abbas Rahimi, T. Simunic
{"title":"Resistive configurable associative memory for approximate computing","authors":"M. Imani, Abbas Rahimi, T. Simunic","doi":"10.3850/9783981537079_0454","DOIUrl":"https://doi.org/10.3850/9783981537079_0454","url":null,"abstract":"Modern computing machines are increasingly characterized by large scale parallelism in hardware (such as GPGPUs) and advent of large scale and innovative memory blocks. Parallelism enables expanded performance tradeoffs whereas memories enable reuse of computational work. To be effective, however, one needs to ensure energy efficiency with minimal reuse overheads. In this paper, we describe a resistive configurable associative memory (ReCAM) that enables selective approximation and asymmetric voltage overscaling to manage delivered efficiency. The ReCAM structure matches an input pattern with pre-stored ones by applying an approximate search on selected bit indices (bitline-configurable) or selective pre-stored patterns (row-configurable). To further reduce energy, we explore proper ReCAM sizing, various configurable search operations with low overhead voltage overscaling, and different ReCAM update policies. Experimental result on the AMD Southern Islands GPUs for eight applications shows bitline-configurable and row-configurable ReCAM achieve on average to 43.6% and 44.5% energy savings with an acceptable quality loss of 10%.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123111637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
Analytical design optimization of sub-ranging ADC based on stochastic comparator 基于随机比较器的子测距ADC分析设计优化
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0105
M. Hossain, T. Iizuka, T. Nakura, K. Asada
{"title":"Analytical design optimization of sub-ranging ADC based on stochastic comparator","authors":"M. Hossain, T. Iizuka, T. Nakura, K. Asada","doi":"10.3850/9783981537079_0105","DOIUrl":"https://doi.org/10.3850/9783981537079_0105","url":null,"abstract":"An optimal design method for a sub-ranging Analog to Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random fluctuations in the comparator offset voltage. The proposed performance model is based on a simple but rigorous Probability Density Function (PDF) for the effective resolution of a stochastic comparator. It is possible to approximate the yield of a stochastic comparator by assuming that the correlations among different analog steps of the output transfer function are negligible. Comparison with Monte Carlo simulation shows that the proposed model precisely estimates the yield of the ADC when it is designed for a reasonable target yield of > 0.8, which is the most practical case while designing a high performance ADC. Application of this model to a stochastic comparator reveals that an additional calibration can significantly enhance the resolution, i.e. it can increase the Number of Bits (NOB) by approximately 2 bits under the same chip yield. Extending the model to a stochastic-comparator-based sub-ranging ADC indicates that the ADC design parameters can be tuned to find the optimal resource distribution between the deterministic coarse stage and the stochastic fine stage.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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