2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)最新文献

Electrothermal simulation of bonding wire degradation under uncertain geometries 不确定几何形状下焊线退化的电热模拟

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0776

T. Casper, H. Gersem, R. Gillon, T. Gotthans, T. Kratochvil, P. Meuris, S. Schöps

引用次数: 13

Mantissa-masking for energy-efficient floating-point LTE uplink MIMO baseband processing 高能效浮点LTE上行MIMO基带处理的尾数掩蔽

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0389

D. Günther, T. Henriksson, R. Leupers, G. Ascheid

引用次数: 1

A fully-digital EM pulse detector 全数字电磁脉冲探测器

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0164

David El-Baze, J. Rigaud, P. Maurine

引用次数: 14

Estimating delay differences of arbiter PUFs using silicon data 利用硅数据估计仲裁puf的延迟差异

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0926

S. Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, C. Kim, K. Parhi

{"title":"Estimating delay differences of arbiter PUFs using silicon data","authors":"S. Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, C. Kim, K. Parhi","doi":"10.3850/9783981537079_0926","DOIUrl":"https://doi.org/10.3850/9783981537079_0926","url":null,"abstract":"This paper presents a novel approach to estimate delay differences of each stage in a standard MUX-based physical unclonable function (PUF). Test data collected from PUFs fabricated using 32 nm process are used to train a linear model. The delay differences of the stages directly correspond to the model parameters. These parameters are trained by using a least mean square (LMS) adaptive algorithm. The accuracy of the response using the proposed model is around 97.5% and 99.5% for two different PUFs. Second, the PUF is also modeled by a perceptron. The perceptron has almost 100% classification accuracy. A comparison shows that the perceptron model parameters are scaled versions of the model derived by the LMS algorithm. Thus, the delay differences can be estimated from the perceptron model where the scaling factor is computed by comparing the models of the LMS algorithm and the perceptron. Because the delay differences are challenge independent, these parameters can be stored on the server. This will enable the server to issue random challenges whose responses need not be stored. An analysis of the proposed model confirms that the delay differences of all stages of the PUFs on the same chip belong to the same Gaussian probability density function.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123764060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Current based PUF exploiting random variations in SRAM cells 基于电流的PUF利用SRAM细胞的随机变化

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0791

Fengchao Zhang, Shuo Yang, J. Plusquellic, S. Bhunia

{"title":"Current based PUF exploiting random variations in SRAM cells","authors":"Fengchao Zhang, Shuo Yang, J. Plusquellic, S. Bhunia","doi":"10.3850/9783981537079_0791","DOIUrl":"https://doi.org/10.3850/9783981537079_0791","url":null,"abstract":"Physical Unclonable Function (PUF) is a security primitive that has been proven to be effective in diverse security solutions ranging from hardware authentication to on-die entropy generation. PUFs can be implemented in a design in two possible ways: (1) adding a separate dedicated circuit; and (2) reusing an existing on-chip structure for generating random signatures. A large percentage of existing PUFs falls into the first category, which suffers from the important drawback of often unacceptable hardware and design overhead. Moreover, they cannot be applied to legacy designs, which do not allow insertion of additional circuit structures. Intrinsic PUFs, that rely on pre-existing circuit structures, such as static random-access memory (SRAM), fall into the second category. They, however, typically suffer from poor entropy as well as lack of robustness. In this paper, we introduce a novel PUF implementation of the second category that exploits the effect of manufacturing process variations in SRAM read access current. In particular, we note that transistor level variations in SRAM cells cause significant variations in the read current and the variation changes with the stored content in a SRAM cell. We propose a method to transform the analog read current value for an SRAM array into robust binary signatures. The proposed PUF can be easily employed for authentication of commercial SRAM chips without any design modification. Furthermore, it can be realized, with minor hardware modification, into chips with embedded memory, e.g., a processor, for on-die entropy generation. Simulation results at 45nm CMOS process for 1000 chips as well as measurement results based on 30 commercial SRAM chips, show promising randomness, uniqueness and robustness under environmental fluctuations.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114914454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation AMS电路的正交信号建模和运算计算，实现快速准确的系统仿真

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0090

L. Gil, M. Radetzki

{"title":"Orthogonal signal modeling and operational computation of AMS circuits for fast and accurate system simulation","authors":"L. Gil, M. Radetzki","doi":"10.3850/9783981537079_0090","DOIUrl":"https://doi.org/10.3850/9783981537079_0090","url":null,"abstract":"We present a general mathematical model of signals for efficient and accurate simulation of analog and mixed signal (AMS) systems. It relies on signal coding and parameterization and allows heterogeneous system specification at different abstraction levels, as well as, the operational computation of continuous time systems' dynamical behavior. In particular, we derive a matrix for operational subdivision of continuous signals and use it to capture accurately the interaction between continuous and discrete time systems. A key advantage of this signal representation is that continuous signal monitoring and analysis can be performed more efficiently, speeding up system verification. We implemented the proposed modeling approach in SystemC AMS 2.0 to exploit the dynamic reactive behavior of TDF MoC for accurate synchronization between the digital and analog system parts. With the example of a PLL system we evaluate the capabilities of our implementation to cope with heterogeneous designs at different design abstraction levels. The experimental results show a significant simulation speedup for high accurate models.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115090347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

ATHENIS_3D: Automotive tested high-voltage and embedded non-volatile integrated SoC platform with 3D technology ATHENIS_3D:采用3D技术的汽车测试高压嵌入式非易失性集成SoC平台

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_1015

E. Wachmann, S. Saponara, C. Zambelli, P. Tisserand, J. Charbonnier, T. Erlbacher, S. Gruenler, C. Hartler, J. Siegert, P. Chassard, D. Ton, L. Ferrari, L. Fanucci

{"title":"ATHENIS_3D: Automotive tested high-voltage and embedded non-volatile integrated SoC platform with 3D technology","authors":"E. Wachmann, S. Saponara, C. Zambelli, P. Tisserand, J. Charbonnier, T. Erlbacher, S. Gruenler, C. Hartler, J. Siegert, P. Chassard, D. Ton, L. Ferrari, L. Fanucci","doi":"10.3850/9783981537079_1015","DOIUrl":"https://doi.org/10.3850/9783981537079_1015","url":null,"abstract":"The ATHENIS_3D FP7 EU project aims at providing new enabling technologies (analog, digital and power components) for high-voltage and high-temperature applications, tested for power systems of new hybrid/electrical vehicles. Innovation is exploited at process/device level (3D chip stacking, wafer level packaging, trench capacitors and TSV-inductors integrated in the interposer, high-reliable non-volatile Magnetic RAM), circuit-level (inductorless high-voltage DC-DC converter, high-temperature 28nm System-on-Chip platform) and system-level (compact 3D embedded power mechatronic system). Enabling high integration levels of complex systems, operating in harsh environments, in a single packaged 3D device, ATHENIS_3D allows for one order of magnitude area reduction vs. today PCB-based power and control systems. Integration costs will be consequently reduced in key industrial sectors for Europe where high-voltage/temperature operations are mandatory (vehicles, avionics, space/defense, industrial automation, energy).","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116526527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

AUTOSAR-based communication coprocessor for automotive ECUs 基于autosar的汽车ecu通信协处理器

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0374

Ahmed Hamed, M. Safar, M. El-Kharashi, A. Salem

引用次数: 2

Adaptive multi-voltage scaling in wireless NoC for high performance low power applications 用于高性能低功耗应用的无线NoC自适应多电压缩放

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0710

H. Mondal, G. Harsha, Raghav Kishore, Sujay Deb

{"title":"Adaptive multi-voltage scaling in wireless NoC for high performance low power applications","authors":"H. Mondal, G. Harsha, Raghav Kishore, Sujay Deb","doi":"10.3850/9783981537079_0710","DOIUrl":"https://doi.org/10.3850/9783981537079_0710","url":null,"abstract":"Networks-on-Chip (NoCs) have garnered significant interest as communication backbone for multicore processors used across a wide range of fields that demand higher computation capability. Wireless NoCs (WNoCs) by augmenting single hop, long range wireless links with wired interconnects; offer the most promising solution to reduce multi-hop long distance communication bottlenecks and opens up innumerable possibilities of topological innovations that are not possible otherwise. However, energy consumption in routers along with Wireless Interface (WI) components still remains considerably high. Specifically for large systems with many nodes in the network, a significant amount of energy is consumed by the communication infrastructure (routers, links, WIs). The usage of the routers and WIs are application dependent and for most cases performance requirements can be met without operating the whole communication infrastructure to its maximum limit. Dynamic reconfigurable systems that can switch between both high performance and low power modes can cater to wide range of applications. In this paper, we propose a novel design methodology for energy efficient WNoC using Adaptive Multi-voltage Scaling (AMS) that reduces dynamic power consumption, along with power gating to prevent static power dissipation in routers and WIs. We evaluate our proposed design in presence of real and synthetic traffic patterns. This approach saves up to 62.50% of static power with less than 1% area overhead. In different traffic scenarios, the proposed WNoC reduces overall packet energy dissipation up to 35% on average compared to a regular WNoC, without significant performance degradation. Design considerations for augmenting existing WNoCs with these routers and corresponding overheads are also presented.","PeriodicalId":311352,"journal":{"name":"2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122461559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Root-cause analysis for memory-locked errors 内存锁定错误的根本原因分析

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Pub Date : 2016-03-14 DOI: 10.3850/9783981537079_0465

John Adler, Djordje Maksimovic, A. Veneris

引用次数: 0