Analytical design optimization of sub-ranging ADC based on stochastic comparator

Abstract

An optimal design method for a sub-ranging Analog to Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random fluctuations in the comparator offset voltage. The proposed performance model is based on a simple but rigorous Probability Density Function (PDF) for the effective resolution of a stochastic comparator. It is possible to approximate the yield of a stochastic comparator by assuming that the correlations among different analog steps of the output transfer function are negligible. Comparison with Monte Carlo simulation shows that the proposed model precisely estimates the yield of the ADC when it is designed for a reasonable target yield of > 0.8, which is the most practical case while designing a high performance ADC. Application of this model to a stochastic comparator reveals that an additional calibration can significantly enhance the resolution, i.e. it can increase the Number of Bits (NOB) by approximately 2 bits under the same chip yield. Extending the model to a stochastic-comparator-based sub-ranging ADC indicates that the ADC design parameters can be tuned to find the optimal resource distribution between the deterministic coarse stage and the stochastic fine stage.