Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)最新文献_第5页

New FPGA architecture for bit-serial pipeline datapath 位串行管道数据通路的FPGA新架构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707881

A. Ohta, T. Isshiki, H. Kunieda

引用次数: 11

Implementing C algorithms in reconfigurable hardware using C2Verilog 使用C2Verilog在可重构硬件中实现C算法

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707944

D. Soderman, Yuri Panchul

引用次数: 38

A FPGA-based custom computing system for solving the assignment problem 一种基于fpga的自定义计算系统

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707924

D. Hung, Jun Wang

引用次数: 3

A scaleable FIR filter using 32-bit floating-point complex arithmetic on a configurable computing machine 在可配置计算机上使用32位浮点复数算法的可伸缩FIR滤波器

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707941

Al Walters, P. Athanas

引用次数: 11

An overview of the COBRA-ABS high level synthesis system for multi-FPGA systems 针对多fpga系统的COBRA-ABS高级综合系统概述

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707888

A. A. Duncan, D. C. Hendry, P. Gray

引用次数: 32

Accelerating Boolean satisfiability with configurable hardware 加速布尔可配置硬件的可满足性

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707896

Peixin Zhong, M. Martonosi, P. Ashar, S. Malik

{"title":"Accelerating Boolean satisfiability with configurable hardware","authors":"Peixin Zhong, M. Martonosi, P. Ashar, S. Malik","doi":"10.1109/FPGA.1998.707896","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707896","url":null,"abstract":"This paper describes and evaluates methods for implementing formula-specific Boolean satisfiability (SAT) solver circuits in configurable hardware. Starting from a general template design, our approach automatically generates VHDL for a circuit that is specific to the particular Boolean formula being solved. Such an approach tightly customizes the circuit to a particular problem instance. Thus, it represents an ideal use for dynamically-reconfigurable hardware, since it would be impractical to fabricate an ASIC for each Boolean formula being solved. Our approach also takes advantage of direct gate mappings and large degrees of fine-grained parallelism in the algorithm's Boolean logic evaluations. We compile our designs to two hardware targets: an IKOS logic emulation system, and Digital SRC's Pamette configurable computing board. Performance evaluations on the DIMACS SAT benchmark suite indicate that our approach offers speedups from 17X to more than a thousand times. Overall, this SAT solver demonstrates promising performance speedups on an important and complex problem with extensive applications in the CAD and AI communities.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133623240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 84

A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing 模糊ART神经网络实现的比较分析:可重构计算的优势

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707927

P. Poiré, Marc-André Cantin, Hervé Daniel, Y. Blaquière, Y. Savaria

引用次数: 0

RVC-a reconfigurable coprocessor for vector processing applications 矢量处理应用的可重构协处理器

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707906

J. Alves, J. S. Matos

引用次数: 8

The NAPA adaptive processing architecture NAPA自适应处理体系结构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707878

Charlé R. Rupp, Mark Landguth, T. Garverick, Edson Gomersall, H. Holt, J. Arnold, M. Gokhale

引用次数: 168

Dynamic circuit generation for solving specific problem instances of Boolean satisfiability 求解布尔可满足性具体问题实例的动态电路生成

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707897

Azra Rashid, J. Leonard, W. Mangione-Smith

引用次数: 35