Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)最新文献_第4页

Specifying and compiling applications for RaPiD 为RaPiD指定和编译应用程序

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707889

Darren C. Cronquist, Paul Franklin, Stefan G. Berg, C. Ebeling

{"title":"Specifying and compiling applications for RaPiD","authors":"Darren C. Cronquist, Paul Franklin, Stefan G. Berg, C. Ebeling","doi":"10.1109/FPGA.1998.707889","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707889","url":null,"abstract":"Efficient, deeply pipelined implementations exist for a wide variety of important computation-intensive applications, and many special-purpose hardware machines have been built that take advantage of these pipelined computation structures. While these implementations achieve high performance, this comes at the expense of flexibility. On the other hand, flexible architectures proposed thus far have not been very efficient. RaPiD is a reconfigurable pipelined datapath architecture designed to provide a combination of performance and flexibility for a variety of applications. It uses a combination of static and dynamic control to efficiently implement pipelined computations. This control, however, is very complicated; specifying a computation's control circuitry directly would be prohibitively difficult. This paper describes how specifications of a pipelined computation in a suitably high-level language are compiled into the control required to implement that computation in the RaPiD architecture. The compiler extracts a statically configured datapath from this description, identifies the dynamic control signals required to execute the computation, and then produces the control program and decoding structure that generates these dynamic control signals.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126552415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 111

A re-evaluation of the practicality of floating-point operations on FPGAs fpga上浮点运算的实用性再评估

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707898

W. Ligon, S. McMillan, G. Monn, Kevin Schoonover, F. Stivers, K. Underwood

引用次数: 141

Exploring optimal cost-performance designs for Raw microprocessors 探索Raw微处理器的最佳性价比设计

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707877

C. A. Moritz, D. Yeung, A. Agarwal

{"title":"Exploring optimal cost-performance designs for Raw microprocessors","authors":"C. A. Moritz, D. Yeung, A. Agarwal","doi":"10.1109/FPGA.1998.707877","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707877","url":null,"abstract":"The semiconductor industry roadmap projects that advance in VLSI technology will permit more than one billion transistors on a chip by the year 2010. The MIT Raw microprocessor is a proposed architecture that strives to exploit these chip-level resources by implementing thousands of tiles, each comprising a processing element and a small amount of memory, coupled by a static two-dimensional interconnect. A compiler partitions fine-grain instruction-level parallelism across the tiles and statically schedules inter-tile communication over the interconnect. Because Raw microprocessors fully expose their internal hardware structure to the software, they can be viewed as a gigantic FPGA with coarse-grained tiles, in which software orchestrates communication over static interconnections. One open challenge in Raw architectures is to determine their optimal grain size and balance. The grain size is the area of each tile, and the balance is the proportion of area in each tile devoted to memory, processing, communication, and I/O. If the total chip area is fixed, more area devoted to processing will result in a higher processing power per node, but will lead to a fewer number of tiles. This paper presents an analytical framework using which designers can reason about the design space of Raw microprocessors. Based on an architectural model and a VLSI cost analysis, the framework computes the performance of applications, and uses an optimization process to identify designs that will execute these applications most cost-effectively.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121640252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 35

Digit-serial DSP library for optimized FPGA configuration 数字串行DSP库优化FPGA配置

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707936

Hanho Lee, G. Sobelman

引用次数: 6

An effective design system for dynamically reconfigurable architectures 一个有效的动态可重构结构设计系统

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707932

S. Govindarajan, Iyad Ouaiss, Meenakshi Kaul, V. Srinivasan, R. Vemuri

引用次数: 30

A run-time reconfigurable engine for image interpolation 一个运行时可重构的图像插值引擎

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707886

R. D. Hudson, D. Lehn, P. Athanas

引用次数: 71

Hardware implementation of generalized profile search on the GENSTORM machine GENSTORM机器上广义轮廓搜索的硬件实现

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707921

E. Mosanya, Jean-Michel Puiatti, E. Sanchez

引用次数: 3

An FPGA implementation of GENET for solving graph coloring problems 用于解决图形着色问题的GENET的FPGA实现

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707918

T. Lee, P. Leong, K. Lee, K. Chan, S. K. Hui, H. K. Yeung, M. Lo, Jimmy Ho-man Lee

引用次数: 7

Automating production of run-time reconfigurable designs 运行时可重构设计的自动化生产

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707892

N. Shirazi, W. Luk, P. Cheung

引用次数: 90

Circlets: circuits as applets 电路:小程序形式的电路

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707925

G. Brebner

引用次数: 16