Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)最新文献_第7页

A variable long-precision arithmetic unit design for reconfigurable coprocessor architectures 一种可重构协处理器结构的可变长精度算术单元设计

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707899

A. Tenca, M. Ercegovac

引用次数: 24

Analysis of the XC6000 architecture for embedded system design 分析XC6000的体系结构，用于嵌入式系统的设计

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707902

K. Weiß, Ronny Kistner, A. Kunzmann, W. Rosenstiel

引用次数: 13

A reconfigurable multiplier array for video image processing tasks, suitable for embedding in an FPGA structure 用于视频图像处理任务的可重构乘法器阵列，适合嵌入在FPGA结构中

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707900

S. D. Haynes, P. Cheung

引用次数: 31

Implementation of RNS addition and RNS multiplication into FPGAs 在fpga中实现RNS加法和RNS乘法

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707940

L. Maltar, F. França, V. Alves, C. L. Amorim

引用次数: 8

An embedded DRAM-FPGA chip with instantaneous logic reconfiguration 具有瞬时逻辑重构的嵌入式DRAM-FPGA芯片

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1900-01-01 DOI: 10.1109/FPGA.1998.707909

M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, M. Yamashina

{"title":"An embedded DRAM-FPGA chip with instantaneous logic reconfiguration","authors":"M. Motomura, Y. Aimoto, A. Shibayama, Y. Yabe, M. Yamashina","doi":"10.1109/FPGA.1998.707909","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707909","url":null,"abstract":"Reconfigurable computing is attracting wide attention as a novel general purpose computing paradigm for accelerating compute intensive and/or data-parallel applications, such as compression, encryption, searching, sorting, and image processing. A key enabling technology for a reconfigurable computer is in-system logic reconfiguration of SRAM-based FPGAs, through which its hardware architecture is dynamically customized for a specific task on demand. Quicker a reconfiguration is, more frequent the reconfigurations can become: i.e., a reconfigurable computer can adapt to applications which have more dynamic behavior. A whole-chip reconfiguration in conventional FPGAs, however, takes at least 100/spl mu/s. With this long latency, a reconfigurable computer is adaptable only to static applications, substantially losing the general-purposeness of the original concept. Integrating a DRAM with an FPGA can become an ideal solution to this problem. The on-chip DRAM can store hundreds of configuration programs, and the logic reconfiguration can get extremely faster by context-switching among the programs utilizing huge bandwidth internal to the DRAM core. Being driven by this observation, we have conducted prototype design of an embedded DRAM-FPGA chip.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116909571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 37