Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)最新文献_第6页

Dynamic circuit generation for solving specific problem instances of Boolean satisfiability 求解布尔可满足性具体问题实例的动态电路生成

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707897

Azra Rashid, J. Leonard, W. Mangione-Smith

引用次数: 35

Reconfigurable hardware as shared resource for parallel threads 作为并行线程共享资源的可重构硬件

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707935

G. Haug, W. Rosenstiel

{"title":"Reconfigurable hardware as shared resource for parallel threads","authors":"G. Haug, W. Rosenstiel","doi":"10.1109/FPGA.1998.707935","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707935","url":null,"abstract":"Approaches to use FPGAs as reconfigurable coprocessors so far always suffered from two problems. First, the hardware required for communication with the host processor occupied an unacceptable large part of the resources available on the FPGA and second, this communication was so slow that the gained acceleration came to naught. The new Xilinx XC6200 family aims to solve both of these problems. The chips are accessed via an SRAM interface, i.e. the host sees them as part of its memory. Besides the configuration bits, which determine logical behaviour and routing, all internal hip-hops of the XC6200 are accessible for reading as well as for writing. This ensures a high performance, since a 32 bit input or output value can be exchanged between the host and the coprocessor by a single load or store operation. In order to make use of the hardware features of the new Xilinx chip series in workstations and PCs easily, a system is presented which synthesizes hardware out of threads coded in C. The threads are part of the C-program running on the host processor. In this paper this system is referred as the Hardware Thread System (HTS). The run time environment required is called the Universal Coprocessor System (UCS). As hardware platform, a specially designed PCI card is used. Besides the reconfigurable coprocessor XC62xx, it consists of the controller (XC4013e) and buffer/data RAM. The RAM of the card can be mapped into the memory address space of the host; nontheless the controller can transfer data between reconfigurable coprocessor and buffer RAM without disturbing the host.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130529275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

The NAPA adaptive processing architecture NAPA自适应处理体系结构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707878

Charlé R. Rupp, Mark Landguth, T. Garverick, Edson Gomersall, H. Holt, J. Arnold, M. Gokhale

引用次数: 168

The systolic array genetic algorithm, an example of systolic arrays as a reconfigurable design methodology 收缩阵列遗传算法，收缩阵列作为可重构设计方法的一个例子

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707907

I. Bland, G. Megson

引用次数: 26

Configuration compression for the Xilinx XC6200 FPGA Xilinx XC6200 FPGA的配置压缩

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707891

S. Hauck, Zhiyuan Li, E. Schwabe

引用次数: 150

Dynamic reconfiguration to support concurrent applications 动态重新配置以支持并发应用程序

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707926

Jack S. N. Jean, K. Tomko, Vikram Yavagal, J. Shah, Robert Cook

引用次数: 71

Frequency-domain sonar processing in FPGAs and DSPs fpga和dsp中的频域声纳处理

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707928

P. Graham, B. Nelson

{"title":"Frequency-domain sonar processing in FPGAs and DSPs","authors":"P. Graham, B. Nelson","doi":"10.1109/FPGA.1998.707928","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707928","url":null,"abstract":"Beamforming is a spatial filtering operation performed on data received by an array of sensors, such as antennas, microphones, or hydrophones. It provides a system with the ability to \"listen\" directionally even when the individual sensors in the array are omnidirectional. Over the past year we have been exploring the use of FPGA based custom computing machines for several sonar beamforming applications, including time domain beamforming (P. Graham nd B. Nelson, 1998), frequency domain beamforming, and matched field processing. In many ways sonar processing fits the criteria found by W. Mangione-Smith and B. Hutchings (1997) for good FPGA applications-the computations are data parallel, they require little control, the data sets are large (infinite streams), and the raw sensor data is at most 12 bits. However, they have three characteristics which make them challenging. First, they involve intensive arithmetic (multiply accumulates and trigonometric functions) on real and/or complex data. Second, they require significant memory support, far beyond that indicated in much previously published work. Third, the scale of the computation is large, requiring (possibly) hundreds of FPGAs and high bandwidth interconnections to meet real time constraints. We address the first issue.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126642310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Architecture and design of GE1, an FCCM for Golomb ruler derivation 用于Golomb标尺推导的FCCM GE1的结构与设计

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707880

A. Dollas, E. Sotiriades, Apostolos Emmanouelides

引用次数: 6

A prototype system for rapid application development using dynamically reconfigurable hardware 一个使用动态可重构硬件进行快速应用开发的原型系统

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707916

J. Ferreira, J. S. Matos

引用次数: 1

50 kHz pattern recognition on the large FPGA processor Enable++ 在大型FPGA处理器上实现50 kHz模式识别

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707908

A. Kugel, K. Kornmesser, R. Lay, J. Ludvig, R. Männer, K. Noffz, S. Rühl, M. Sessler, H. Simmler, H. Singpiel

引用次数: 4