Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)最新文献

Mapping the MD5 hash algorithm onto the NAPA architecture 将MD5哈希算法映射到NAPA架构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707910

J. Arnold

引用次数: 4

Plastic cell architecture: towards reconfigurable computing for general-purpose 塑料单元结构:面向通用的可重构计算

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707883

Kouichi Nagami, K. Oguri, Tsunemichi Shiozawa, Hideyuki Ito, Ryusuke Konishi

引用次数: 25

High level synthesis for designing custom computing hardware 设计自定义计算硬件的高级综合

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707938

Goran Doncev, M. Leeser, Shantanu Tarafdar

引用次数: 12

JHDL-an HDL for reconfigurable systems 用于可重构系统的一种HDL

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707895

P. Bellows, B. Hutchings

{"title":"JHDL-an HDL for reconfigurable systems","authors":"P. Bellows, B. Hutchings","doi":"10.1109/FPGA.1998.707895","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707895","url":null,"abstract":"JHDL is a design tool for reconfigurable systems that allows designers to express circuit organizations that dynamically change over time in a natural way, using only standard programming abstractions found in object-oriented languages. JHDL manages FPGA resources in a manner that is similar to the way object-oriented languages manage memory: circuits are treated as distinct objects and a circuit is configured onto a configurable computing machine (CCM) by invoking its constructor effectively \"constructing \" an instance of the circuit onto the reconfigurable platform just as object instances are allocated in memory with conventional object-oriented languages. This approach of using object constructors/destructors to control the circuit lifetime on a CCM is a powerful technique that naturally leads to a dual simulation/execution environment where a designer can easily switch between either software simulation or hardware execution on a CCM with a single application description. Moreover JHDL supports dual hardware/software execution; parts of the application described using JHDL circuit constructs can be executed on the CCM while the remainder of the application the-GUI for example-can run on the CCM host. Based on an existing programming language (Java), JHDL requires no language extensions and can be used with any standard Java 1.1 distribution.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114800862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 309

The design and implementation of a context switching FPGA 上下文切换FPGA的设计与实现

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707884

Stephen M. Scalera, J. R. Vázquez

引用次数: 185

PAM-Blox: high performance FPGA design for adaptive computing PAM-Blox:用于自适应计算的高性能FPGA设计

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707894

O. Mencer, M. Morf, M. Flynn

{"title":"PAM-Blox: high performance FPGA design for adaptive computing","authors":"O. Mencer, M. Morf, M. Flynn","doi":"10.1109/FPGA.1998.707894","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707894","url":null,"abstract":"PAM-Blox are object-oriented circuit generators on top of the PCI Pamette design environment, PamDC. High-performance FPGA design for adaptive computing is simplified by using a hierarchy of optimized hardware objects described in C++. PAM-Blox consist of two major layers of abstraction. First, PamBlox are parameterizable simple elements such as counters and adders. Automatic placement of carry chains and flexible shapes are supported. PaModules are more complex elements possibly instantiating PamBlox. PaModules have fixed shapes and are usually optimized for a specific data-width. Examples for PaModules are multipliers, Coordinate Rotations (CORDICs), and special arithmetic units for encryption. The key difference of our approach to most other design tools for FPGAs is that the designer has total control over placement at each level of the design hierarchy, which is the key to high-performance FPGA design. Second, the object interface was chosen carefully to encourage code-reuse and simplify code-sharing between designers. PAM-Blox are intended to be part of an open library that allows design sharing between members of the adaptive computing community.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131233798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 109

Some applications of FPGAs in bio-inspired hardware fpga在仿生硬件中的一些应用

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707915

A. Stauffer, M. Sipper, A. Pérez-Uribe

引用次数: 2

SLAAC: a distributed architecture for adaptive computing SLAAC:用于自适应计算的分布式体系结构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707919

S. Crago, Brian Schott, R. Parker

引用次数: 8

Benchmarking technology for configurable computing system 可配置计算系统的基准测试技术

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707913

S. Kumar, Luiz Pires, D. Pandalai, M. Vojta, J. Golusky, S. Wadi, H. Spaanenburg

引用次数: 6

Scalable network based FPGA accelerators for an automatic target recognition application 基于可扩展网络的FPGA加速自动目标识别应用

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707917

Ruth Sivilotti, Young H. Cho, Wen-King Su, D. Cohen, Brian Bray

{"title":"Scalable network based FPGA accelerators for an automatic target recognition application","authors":"Ruth Sivilotti, Young H. Cho, Wen-King Su, D. Cohen, Brian Bray","doi":"10.1109/FPGA.1998.707917","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707917","url":null,"abstract":"Image processing, specifically automatic target recognition (ATR) in synthetic aperture radar (SAR) imagery, is an application area that can require tremendous processing throughput. In this application, data comes from high bandwidth sensors, where the processing is time-critical. There is limited space and power for processing the data in the sensor platforms or in battlefield groundstations. DoD's strong push for using commercial-off-the-shelf (COTS) technology, the very high non-recurring engineering (NRE) costs for low volume ASICs, and evolving algorithms limit the feasibility of using custom special purpose hardware. In addition, a scalable system is required as the different sensor platforms have different image pixel rates and different mission requirements have different target recognition throughput needs per pixel. In this paper, we describe an ATR algorithm implementation using FPGA accelerators. We first describe the ATR algorithm that was implemented, the implementation on a single FPGA, how the FPGA nodes are connected to make a scalable system, and compare the performance to current scalable microprocessor-based implementations.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123685061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11