将MD5哈希算法映射到NAPA架构

J. Arnold
{"title":"将MD5哈希算法映射到NAPA架构","authors":"J. Arnold","doi":"10.1109/FPGA.1998.707910","DOIUrl":null,"url":null,"abstract":"National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. In the NAPA1000 the FIP is a small 32-bit RISC microprocessor and the ALP is a 64/spl times/96 array of fine grain reconfigurable logic cells. The NAPA1000 also contains two banks of 2048/spl times/32 Pipeline Memory Array (PMA), eight banks of 256/spl times/8 Scratchpad Memory Array (SMA), and one bank of 1024/spl times/32 Local Memory Array (LMA). External to the NAPA1000 are two banks of DRAM and an interface to a host computer. The Toggle Bus transceiver is the interface to a multi-stage interconnect network, and is capable of performing arbitrary reflections and rotations on 32-bit words. The Reconfiguration Pipeline Control unit (RPC) can also serve as a DMA engine.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Mapping the MD5 hash algorithm onto the NAPA architecture\",\"authors\":\"J. Arnold\",\"doi\":\"10.1109/FPGA.1998.707910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. In the NAPA1000 the FIP is a small 32-bit RISC microprocessor and the ALP is a 64/spl times/96 array of fine grain reconfigurable logic cells. The NAPA1000 also contains two banks of 2048/spl times/32 Pipeline Memory Array (PMA), eight banks of 256/spl times/8 Scratchpad Memory Array (SMA), and one bank of 1024/spl times/32 Local Memory Array (LMA). External to the NAPA1000 are two banks of DRAM and an interface to a host computer. The Toggle Bus transceiver is the interface to a multi-stage interconnect network, and is capable of performing arbitrary reflections and rotations on 32-bit words. The Reconfiguration Pipeline Control unit (RPC) can also serve as a DMA engine.\",\"PeriodicalId\":309841,\"journal\":{\"name\":\"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/FPGA.1998.707910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/FPGA.1998.707910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4

摘要

国家半导体公司的自适应处理架构(NAPA)将一个固定指令集处理器(FIP)、一个自适应逻辑处理器(ALP)、存储器和其他支持电路集成到一个可重构计算设备中。在NAPA1000中,FIP是一个小型的32位RISC微处理器,而ALP是一个64/spl倍/96的细粒度可重构逻辑单元阵列。NAPA1000还包含两组2048/spl倍/32 Pipeline Memory Array (PMA),八组256/spl倍/8 Scratchpad Memory Array (SMA)和一组1024/spl倍/32 Local Memory Array (LMA)。NAPA1000的外部是两组DRAM和一个到主机的接口。切换总线收发器是多级互连网络的接口,能够在32位字上执行任意反射和旋转。重构管道控制单元(RPC)也可以作为DMA引擎。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Mapping the MD5 hash algorithm onto the NAPA architecture
National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. In the NAPA1000 the FIP is a small 32-bit RISC microprocessor and the ALP is a 64/spl times/96 array of fine grain reconfigurable logic cells. The NAPA1000 also contains two banks of 2048/spl times/32 Pipeline Memory Array (PMA), eight banks of 256/spl times/8 Scratchpad Memory Array (SMA), and one bank of 1024/spl times/32 Local Memory Array (LMA). External to the NAPA1000 are two banks of DRAM and an interface to a host computer. The Toggle Bus transceiver is the interface to a multi-stage interconnect network, and is capable of performing arbitrary reflections and rotations on 32-bit words. The Reconfiguration Pipeline Control unit (RPC) can also serve as a DMA engine.
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