Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)最新文献_第2页

Reconfigurable processor architectures exploiting high bandwidth optical channels 利用高带宽光通道的可重构处理器架构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707914

M. Sakr, S. Levitan, C. Lee Giles, D. Chiarulli

{"title":"Reconfigurable processor architectures exploiting high bandwidth optical channels","authors":"M. Sakr, S. Levitan, C. Lee Giles, D. Chiarulli","doi":"10.1109/FPGA.1998.707914","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707914","url":null,"abstract":"There is growing interest in studying the possibility of reconfigurable architectures as replacements for general purpose computing for certain application domains. Reconfigurable systems can take advantage of deep computational pipelines, perform concurrent execution and are inherently data flow in nature. Furthermore, these systems have the capability of 'on the fly' reconfiguration of all or portions of the hardware to represent all the functionality required to complete the execution of an application. However, these architectures suffer from slow run time reconfiguration (RTR) due to the fact that the configuration memory resides off-chip and hence requires high access latency. This disadvantage limits the system performance and the application domain in which reconfigurable systems could prove effective. To overcome slow RTR, recent approaches include on-chip configuration memory to cache the next possible configurations. This approach trades off die area for fast RTR which diminishes the processing power of the reconfigurable processor. The high cost of adding configuration cache, up to 50% of the die area, would considerably increase the number of hardware reconfigurations required compared to architectures without on-chip cache. This paper presents an alternative reconfigurable architecture which overcomes these limitations by exploiting high bandwidth optical channels. We develop a performance model to analyze and compare the performance of cache based RTR architectures, optical based RTR architectures and hybrid optical-cache based RTR architectures.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124117240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Fast partial reconfiguration for FCCMs fccm的快速局部重构

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707934

S. Sezer, Roger Francis Woods, J. Heron, A. Marshall

{"title":"Fast partial reconfiguration for FCCMs","authors":"S. Sezer, Roger Francis Woods, J. Heron, A. Marshall","doi":"10.1109/FPGA.1998.707934","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707934","url":null,"abstract":"The emergence of new FPGA families such as the Xilinx 6200 FPGA family and the Atmel 40000 series has been an important development in the FPGAs for Custom Computing Machines (FCCMs). These devices have number of appealing features when compared to other technologies such as the Xilinx 4000 series SRAM technology. These can be characterised as follows: faster reconfiguration (typically m/spl mu/ s or /spl mu/s), support for partial reconfiguration, dedicated microprocessor interface. An approach for run-time reconfiguration can be achieved by considering a range of functions collectively and developing the specific circuit architectures for each so that a high degree of commonality exists between them in terms of their structure, wiring and cell function. This is done by representing the functions or algorithms using Signal Flow Graphs (SFGs) and manipulating them to produce similar graphs for different functions. This basic concept can only be exploited through the development of an efficient hardware system. This revolves around the concept of virtual hardware which is integrated within the operating system and is supported by programming languages such as C and C++. The reconfigurable designs which allow partial re-configuration, are stored within a configuration data graph. Whilst this allows the configuration data to be efficiently stored, reconfiguration state graphs are used for high speed reconfiguration. The entire software hardware system for fast partial reconfiguration is illustrated.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130035618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

A stream-based configurable computing radio testbed 一种基于流的可配置计算无线电试验台

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707879

Steven F. Swanchara, S. Harper, P. Athanas

引用次数: 11

A quantitative analysis of reconfigurable coprocessors for multimedia applications 多媒体应用中可重构协处理器的定量分析

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707876

T. Miyamori, K. Olukotun

引用次数: 168

Mapping homogeneous computations onto dynamically configurable coarse-grained architectures 将同构计算映射到动态可配置的粗粒度架构上

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707933

Andreas Dandalis, V. Prasanna

{"title":"Mapping homogeneous computations onto dynamically configurable coarse-grained architectures","authors":"Andreas Dandalis, V. Prasanna","doi":"10.1109/FPGA.1998.707933","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707933","url":null,"abstract":"FPGAs are fine-grained architectures, mainly designed for implementing bit-level tasks and random logic functions. Their performance is limited for computationally demanding applications over large word length data. A highly promising avenue that is being explored by many research groups is coarse-grained configurable architectures. These architectures are datapath-oriented structures and consist of a small number of powerful, word-based configurable processing elements (PEs). Such architectures can result in greater computational efficiency and high throughput for coarse-grained computing tasks. The key for achieving high performance solutions is efficient mapping of tasks onto above architectures. In addition to achieving high computational rates, partitionability is a desirable characteristic of the mapping. Moreover, the computational efficiency must scale with the size of the architecture. Finally, it must result in a simple PE structure, regular/balanced dataflow and sustainable I/O requirements so that it can be realized in hardware. In this paper we show a methodology for deriving dynamic computation structures for 2 dimensioned homogeneous computations. Homogeneous computations lead to all PEs having the same functionality. The derived dynamic structures match the datapath-oriented nature of coarse-grained architectures and lead to efficient mapping schemes. Our solutions require constant I/O and smaller amount of local memory/PE compared with known solutions.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133588510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Self-sorting radix-2 FFT on FPGAs using parallel pipelined distributed arithmetic blocks 基于并行流水线分布式算术块的fpga自排序基数-2 FFT

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707943

Manoucher Shaditalab, G. Bois, M. Sawan

引用次数: 15

Accelerating Adobe Photoshop with reconfigurable logic 加速adobephotoshop与可重构逻辑

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707901

Satnam Singh, Robert Slous

引用次数: 25

Characterization and parameterization of a pipeline reconfigurable FPGA 管道可重构FPGA的特性与参数化

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707923

M. Moe, H. Schmit, S. Goldstein

引用次数: 5

DES key breaking, encryption and decryption on the XC6216 在XC6216上实现DES密钥破解、加密和解密

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707930

T. Kean, Ann Duncan

引用次数: 24

An architecture simulator for National Semiconductor's adaptive processing architecture (NAPA) 国家半导体自适应处理体系结构(NAPA)的体系结构模拟器

Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251) Pub Date : 1998-04-15 DOI: 10.1109/FPGA.1998.707912

J. Arnold

{"title":"An architecture simulator for National Semiconductor's adaptive processing architecture (NAPA)","authors":"J. Arnold","doi":"10.1109/FPGA.1998.707912","DOIUrl":"https://doi.org/10.1109/FPGA.1998.707912","url":null,"abstract":"Early simulation is a very important tool in the development any large scale system. Accuracy and flexibility are critical characteristics which allow the architect to explore the design tradeoff space. Moreover, in many systems, especially those for reconfigurable computing, a good simulation environment will continue to be used long after the architecture solidifies, serving a variety of roles including as a platform for the development of run time systems, programming tools, benchmarks, and even end applications. Therefore, visibility, controllability and user interface are also important design considerations. National Semiconductor's Adaptive Processing Architecture (NAPA) integrates a Fixed Instruction set Processor (FIP), an Adaptive Logic Processor (ALP), memory and other support circuitry into a single reconfigurable computing device. The NAPA architecture simulator, NAPAsim, consists of a C language, cycle accurate model of the RISC core, peripherals and memories, coupled with an event driven logic simulator for modelling the user-defined contents of the reconfigurable logic and a Tcl/Tk based GUI to provide source level symbolic debugging capabilities. NAPAsim was developed to serve as both a tool for architectural exploration and as a platform for system and application software development.","PeriodicalId":309841,"journal":{"name":"Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-04-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131384690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3