Fast partial reconfiguration for FCCMs

Abstract

The emergence of new FPGA families such as the Xilinx 6200 FPGA family and the Atmel 40000 series has been an important development in the FPGAs for Custom Computing Machines (FCCMs). These devices have number of appealing features when compared to other technologies such as the Xilinx 4000 series SRAM technology. These can be characterised as follows: faster reconfiguration (typically m/spl mu/ s or /spl mu/s), support for partial reconfiguration, dedicated microprocessor interface. An approach for run-time reconfiguration can be achieved by considering a range of functions collectively and developing the specific circuit architectures for each so that a high degree of commonality exists between them in terms of their structure, wiring and cell function. This is done by representing the functions or algorithms using Signal Flow Graphs (SFGs) and manipulating them to produce similar graphs for different functions. This basic concept can only be exploited through the development of an efficient hardware system. This revolves around the concept of virtual hardware which is integrated within the operating system and is supported by programming languages such as C and C++. The reconfigurable designs which allow partial re-configuration, are stored within a configuration data graph. Whilst this allows the configuration data to be efficiently stored, reconfiguration state graphs are used for high speed reconfiguration. The entire software hardware system for fast partial reconfiguration is illustrated.