利用高带宽光通道的可重构处理器架构

M. Sakr, S. Levitan, C. Lee Giles, D. Chiarulli
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引用次数: 0

摘要

人们对研究可重构架构替代某些应用领域的通用计算的可能性越来越感兴趣。可重构系统可以利用深度计算管道,执行并发执行,本质上是数据流。此外,这些系统具有“动态”重新配置全部或部分硬件的能力,以表示完成应用程序执行所需的所有功能。然而,由于配置内存位于片外,因此需要很高的访问延迟,这些体系结构的运行时重新配置(RTR)很慢。这一缺点限制了系统性能和可重构系统可以证明有效的应用领域。为了克服慢RTR,最近的方法包括片上配置存储器来缓存下一个可能的配置。这种方法为快速RTR减少了芯片面积,从而降低了可重构处理器的处理能力。与没有片上缓存的架构相比,增加配置缓存的高成本(高达芯片面积的50%)将大大增加所需硬件重新配置的数量。本文提出了一种利用高带宽光通道来克服这些限制的可重构结构。我们建立了一个性能模型来分析和比较基于缓存的RTR架构、基于光的RTR架构和基于混合光缓存的RTR架构的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Reconfigurable processor architectures exploiting high bandwidth optical channels
There is growing interest in studying the possibility of reconfigurable architectures as replacements for general purpose computing for certain application domains. Reconfigurable systems can take advantage of deep computational pipelines, perform concurrent execution and are inherently data flow in nature. Furthermore, these systems have the capability of 'on the fly' reconfiguration of all or portions of the hardware to represent all the functionality required to complete the execution of an application. However, these architectures suffer from slow run time reconfiguration (RTR) due to the fact that the configuration memory resides off-chip and hence requires high access latency. This disadvantage limits the system performance and the application domain in which reconfigurable systems could prove effective. To overcome slow RTR, recent approaches include on-chip configuration memory to cache the next possible configurations. This approach trades off die area for fast RTR which diminishes the processing power of the reconfigurable processor. The high cost of adding configuration cache, up to 50% of the die area, would considerably increase the number of hardware reconfigurations required compared to architectures without on-chip cache. This paper presents an alternative reconfigurable architecture which overcomes these limitations by exploiting high bandwidth optical channels. We develop a performance model to analyze and compare the performance of cache based RTR architectures, optical based RTR architectures and hybrid optical-cache based RTR architectures.
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