Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)最新文献_第7页

A new initial guess for sine function dedicated to sine-output direct digital frequency synthesizers 一个新的初始猜测正弦函数专用于正弦输出直接数字频率合成器

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869821

A. M. Sodagar, G. R. Lahiji

引用次数: 5

Digital processing of Raman spectra for diagnosis of atherosclerosis 拉曼光谱数字处理在动脉粥样硬化诊断中的应用

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869872

A. R. de Paula, C.M.F. Peris, H. Sidaoui, S. Sathaiah

引用次数: 4

The dynamic threshold voltage MOSFET 动态阈值电压MOSFET

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869845

F. J. De la Hidalga-W, M. Deen

引用次数: 7

Power electronics technologies for the new millennium 新千年的电力电子技术

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869867

S. Abedinpour, K. Shenai

引用次数: 10

On the electromagnetic emissions from mobile telephones: standards, instrumentation and probes 移动电话电磁辐射:标准、仪器和探针

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869881

A. Annino, G. De Mercato, A. Raciti, A. Ciccazzo, G. Privitera

引用次数: 0

Gate triggering: a new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization 门触发:在静态CMOS集成电路中最小化故障功耗的新框架及其基于ilp的优化

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869822

N. Mahapatra, R. Janakiraman

{"title":"Gate triggering: a new framework for minimizing glitch power dissipation in static CMOS ICs and its ILP-based optimization","authors":"N. Mahapatra, R. Janakiraman","doi":"10.1109/ICCDCS.2000.869822","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869822","url":null,"abstract":"Glitches are an important source of power dissipation in static CMOS ICs that can contribute to as much as 70% of total power dissipation in certain cases (e.g., arithmetic modules). Although research into various aspects of glitch power dissipation has been undertaken in the past, most approaches to addressing it are ad hoc and limited in their applicability. In this paper, we propose a new framework, gate triggering, for systematically minimizing glitch power dissipation in static CMOSICs. The framework is based on the idea that glitches can be effectively minimized by triggering logic evaluation at a gate only when all of its inputs have stabilized. For this purpose, to every potentially glitchy gate is added a small amount of control logic, which, when enabled, triggers logic evaluation at the gate. A clocked delay chain is employed to generate enable signals at the proper times for all gates to be triggered. We present an integer linear programming (ILP) formulation to minimize the overheads (viz. delay element, control logic, and extra wiring) of our approach subject to a critical-path delay constraint. Application of the new approach to test circuits (such as ripple carry adder and array multiplier) in 1.2 /spl mu/ technology yields 95% or more elimination of glitch power dissipation with negligible area and timing overheads after optimization. An added advantage of the approach is that short-circuit power dissipation at all triggered gates is also minimized-short-circuit power dissipation in current standard-cell based designs can exceed 50% of the total power dissipation.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125493575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Real-time digit-serial decimating filter using systolic arrays and implemented in a CPLD 实时数字串行抽取滤波器采用收缩阵列，并在CPLD中实现

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869812

D. Iparraguirre-Cardenas, G. F. Santillan-Quinonez

引用次数: 0

A new GCP cell technology for DRAM design 一种新的用于DRAM设计的GCP单元技术

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869828

Harn-Bor Yang, Jyi-Tsong Lin

{"title":"A new GCP cell technology for DRAM design","authors":"Harn-Bor Yang, Jyi-Tsong Lin","doi":"10.1109/ICCDCS.2000.869828","DOIUrl":"https://doi.org/10.1109/ICCDCS.2000.869828","url":null,"abstract":"A GCP (Gate-Contact-Plate) cell for a high density, high performance DRAM has been proposed. The cell made in a P-well consists of an n-channel transistor and a capacitor with cell plate being connected to the word line directly to reduce leakage from cell-to-cell and P-N/sup +/ junction. In addition, combining a stack and a trench type to increase the capacitance of the cell forms the capacitor. This cell structure and its electrical analysis are realized and implemented by TMA simulator. The result shows that this cell has a 3.5-/spl mu/m-deep trench and a 7-nm-thick oxide. Based on 16M DRAM design, the GCP and a conventional cell with the same size, which is 1.16/spl times/2.03-/spl mu/m/sup 2/, can have the same capacitance. The GCP cell needs a trench depth 3.5 /spl mu/m whereas that of a conventional cell needs 7 um. Over 50% trench depth is saved and the process to produce the GCP cell becomes easier. Moreover, the leakage between adjacent cells is small enough, even if the cell size is scaled down to 0.8/spl times/1.43-/spl mu/m/sup 2/, compared to that of the conventional one. In addition, the performance of pass transistor is also demonstrated, which shows that the GCP cell can be operated properly in the DRAM circuit. Therefore, it is believed that the GCP cell is a promising candidate for a 64M DRAM and beyond.","PeriodicalId":301003,"journal":{"name":"Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131275881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Efficient and simple hardware realization for broadband GMSK-modulators using PLD-technology to enable MPEG2-transmissions in a standard TV-channel 使用pld技术实现宽带gmsk调制器的高效和简单的硬件实现，使mpeg2在标准电视频道中传输

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869886

C. Heiner

引用次数: 1

A CMOS low voltage, low power continuous-time biquadratic cell 一种CMOS低电压、低功耗连续双二次元电池

Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474) Pub Date : 2000-03-15 DOI: 10.1109/ICCDCS.2000.869807

M. Fedeli

引用次数: 0