A CMOS low voltage, low power continuous-time biquadratic cell

Abstract

A CMOS biquadratic cell with low voltage supply and low power consumption is proposed. To design the circuit a 0.25 /spl mu/m minimum lithography technology has been utilized and a g/sub m/-C configuration has been chosen to implement the basic block of the filter (the integrator). To reach the highest linearity, a fully differential structure has been exploited for the transconductor and, to correctly size it, particular attention to the mismatch problems has been paid. With a voltage supply of 1.2 V and a power consumption of 200 /spl mu/W, the transconductor presents a gain-bandwidth product of 30 MHz. For the biquadratic cell a cut-off frequency of 1 MHz with quality factor Q=1 have been imposed. The filter, with a power dissipation of 1 mW, reaches 1% of THD with 275 mV peak differential sinusoidal input signal, while the total input noise is about 190 /spl mu/V/sub rms/; in conclusion the cell presents a dynamic range of 60 dB and a SNDR peak of 48.6 dB.