A new GCP cell technology for DRAM design

A GCP (Gate-Contact-Plate) cell for a high density, high performance DRAM has been proposed. The cell made in a P-well consists of an n-channel transistor and a capacitor with cell plate being connected to the word line directly to reduce leakage from cell-to-cell and P-N/sup +/ junction. In addition, combining a stack and a trench type to increase the capacitance of the cell forms the capacitor. This cell structure and its electrical analysis are realized and implemented by TMA simulator. The result shows that this cell has a 3.5-/spl mu/m-deep trench and a 7-nm-thick oxide. Based on 16M DRAM design, the GCP and a conventional cell with the same size, which is 1.16/spl times/2.03-/spl mu/m/sup 2/, can have the same capacitance. The GCP cell needs a trench depth 3.5 /spl mu/m whereas that of a conventional cell needs 7 um. Over 50% trench depth is saved and the process to produce the GCP cell becomes easier. Moreover, the leakage between adjacent cells is small enough, even if the cell size is scaled down to 0.8/spl times/1.43-/spl mu/m/sup 2/, compared to that of the conventional one. In addition, the performance of pass transistor is also demonstrated, which shows that the GCP cell can be operated properly in the DRAM circuit. Therefore, it is believed that the GCP cell is a promising candidate for a 64M DRAM and beyond.