{"title":"VEEP - A Vector Editor and Preparer","authors":"S. Gelman","doi":"10.1145/800263.809289","DOIUrl":"https://doi.org/10.1145/800263.809289","url":null,"abstract":"VEEP, a VEctor Editor and Preparer, is an intelligent, interactive editor for the entry and update of test vectors which are the inputs to logic simulation. Since being introduced in Bell Laboratories and Western Electric in February 1981, VEEP has been able to increase the productivity of vector writers more than 25% by providing users a powerful system that reduces much of the job's drudgery, and allows for quick specification and updating of tests.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116341011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Depth-First Branch-and-Bound Algorithm for Optimal PLA Folding","authors":"W. Grass","doi":"10.1145/800263.809198","DOIUrl":"https://doi.org/10.1145/800263.809198","url":null,"abstract":"In this paper we are concerned with the PLA folding problem defined by Hachtel, Newton and Sangiovanni-Vincentelli. We propose a depth first branch and bound procedure for optimizing simultaneous row and column folding. With our procedure one can compute such a PLA folding which is optimal with respect to different practical constraints. We present some results of an implemented algorithm that is restricted to row folding.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126789565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"IBM 3081 System Overview and Technology","authors":"C. Collins","doi":"10.1145/800263.809190","DOIUrl":"https://doi.org/10.1145/800263.809190","url":null,"abstract":"The development of the IBM 3081 established the methodology for designinc and manufacturing a high-performance computer from an LSI chip technology. The high density packaging of the LSI chip is used to minimize interconnections and to support a fast machine cycle time. This paper will describe the methods used and will highlight some of the design problems that were solved, to offer an understanding of the challenges that LSI brings to the design cycle.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127243866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimum Placement of Two Rectangular Blocks","authors":"M. Chandrasekhar, M. Breuer","doi":"10.1145/800263.809303","DOIUrl":"https://doi.org/10.1145/800263.809303","url":null,"abstract":"This paper deals with a special case of the hierarchical layout of custom VLSI circuits. It presents the analysis as well as an algorithm for the placement of two rectangular blocks, where the objective function is to minimize the total layout area including the interconnect space. Block placement transformations, such as translations and rotations are considered. Sharing of tracks by more than one wire segment is also allowed. Extension to the more general case dealing with n blocks is being investigated.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124101677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Techniques for Programmable Logic Array Folding","authors":"G. Hachtel, A. Newton, A. Sangiovanni-Vincentelli","doi":"10.1145/800263.809200","DOIUrl":"https://doi.org/10.1145/800263.809200","url":null,"abstract":"The optimal PLA folding problem is presented and discussed in its different forms. In particular, new algorithms for row folding in unconstrained architectures and in AND-OR-AND architectures are presented and their complexity examined. The problem of finding an optimal row folding after a column folding has been performed, is described and an algorithm for its solution given. Finally, the organization of an APL package for row and column folding of PLA's is introduced and experimental results reported.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"28 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129054364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Computer System Design Description","authors":"Y. Chu","doi":"10.1145/800263.809298","DOIUrl":"https://doi.org/10.1145/800263.809298","url":null,"abstract":"This paper describes language constructs for creating a very high-level language as a tool for computer system design. In order to describe the complexity of a computer system, this language permits descriptions in a heirarchical manner at different levels of system detail and at various cross-sections of system structure. It allows descriptions of system hardware, system software, and the interactions between system hardware and software.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"2022 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114911649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Analytical Method for Compacting Routing Area in Integrated Circuits","authors":"M. Ciesielski, E. Kinnen","doi":"10.1145/800263.809182","DOIUrl":"https://doi.org/10.1145/800263.809182","url":null,"abstract":"An analytical method is proposed for solving a routing area compaction problem in building block integrated circuits. Related minimization is performed with a linear programming technique. Minimum channel dimensions are calculated for a preliminary routing; these dimensions are used to construct routing constraints. Placement constraints are added for the interrelations between placement and routing. This combined set of constraints leads to a least overestimation of routing area and under certain conditions guarantees routing feasibility. Computational complexity and existence of a solution are discussed.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132204202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interactive Design Language: A Unified Approach to Hardware Simulation, Synthesis and Documentation","authors":"L. Maissel, D. Ostapko","doi":"10.1145/800263.809206","DOIUrl":"https://doi.org/10.1145/800263.809206","url":null,"abstract":"IDL is a hardware design language in use in the VLSI environment. It incorporates a significant number of high-level features such as groups, subroutines, and labels and is particularly well adapted to dealing with parallelism at the hardware level. In addition to being human intelligible (and therefore appropriate as a documentation medium), IDL code can be used to generate 2-level logic which, under the IDL system, can be manipulated in a number of ways, including product term factoring and minimization, feedback minimization, partitioning, merging, and verification. The IDL system contains several simulators that are driven by IDL code. The most common embodiment of IDL output in hardware is a PLA.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134127062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Low Cost, Transportable, Data Management System for LSI/VLSI Design","authors":"David C. Smith, Barry S. Wagner","doi":"10.1145/800263.809219","DOIUrl":"https://doi.org/10.1145/800263.809219","url":null,"abstract":"The philosophy, structure, and design of a data-management system that is applicable to a wide range of organizational environments - from production groups to research and development groups - are introduced and discussed. The system is in operation in two locations and has been used to design numerous LSI/VLSI chips. This low cost system is transportable, extendable, and suitable for use by designers having a diversity of CAD-related skill levels. User reaction to the system and future plans are discussed.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134561766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Bellon, A. Liothin, Sylvain Sadier, G. Saucier, R. Velazco, F. Grillot, M. Issenman
{"title":"Automatic Generation of Microprocessor Test Programs","authors":"C. Bellon, A. Liothin, Sylvain Sadier, G. Saucier, R. Velazco, F. Grillot, M. Issenman","doi":"10.1145/800263.809260","DOIUrl":"https://doi.org/10.1145/800263.809260","url":null,"abstract":"This paper presents an automatic generation system for behavioral test programs of microprocessors. First, the test environment is presented, as well as its consequences on test program generation. In the second part, the test principles are outlined; it is a behavioral test, i.e a test determined from the user's description of the microprocessor; the resulting test programs are quite modular. The third part presents the description language and the generation system.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132964845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}