发布求助
文献互助 智能选刊 最新文献

19th Design Automation Conference最新文献

筛选
英文 中文
Developments in Logic Network Path Delay Analysis 逻辑网络路径延迟分析的研究进展
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809265
L. Bening, T. Lane, C. Alexander, James E. Smith
{"title":"Developments in Logic Network Path Delay Analysis","authors":"L. Bening, T. Lane, C. Alexander, James E. Smith","doi":"10.1145/800263.809265","DOIUrl":"https://doi.org/10.1145/800263.809265","url":null,"abstract":"This paper discusses path delay analysis programs as an alternative to detailed logic simulation for finding timing problems in logic networks. Fundamentals of path delay analysis are reviewed, and several previously reported methods are surveyed. This is followed by a more detailed description of a delay analysis program that we have recently implemented. Our implementation uncovers a wide variety of timing problems and has a run time that is linearly proportional to the number of gates in the network. Other principle features are that timing information loss is minimized by treating 0-to-1 and 1-to-0 delays separately, and the user is given the capability of selectively disabling paths in order to discover timing problems that would otherwise remain hidden.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1405 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132163930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing VLSI电路布局验证与布线的元胞图像处理技术
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809256
T. Mudge, Rob A. Rutenbar, R. Lougheed, D. Atkins
{"title":"Cellular Image Processing Techniques for VLSI Circuit Layout Validation and Routing","authors":"T. Mudge, Rob A. Rutenbar, R. Lougheed, D. Atkins","doi":"10.1145/800263.809256","DOIUrl":"https://doi.org/10.1145/800263.809256","url":null,"abstract":"The architecture of the Cytocomputer, an existing special-purpose, pipelined cellular image processor, is described. A formalism used to express cellular operations on images is then given. Cellular image processing algorithms are then developed that perform (1) design rule checks (DRC's) on VLSI circuit layouts, and (2) Lee-type wire routing. Two sets of cellular image processing transformations for checking the Mead and Conway design rules and for Lee-routing have been defined and used to program the Cytocomputer. Some experimental results are shown for these cellular implementations.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133876575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Global Wiring on a Wire Routing Machine 在导线布线机上进行全局布线
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.5555/800263.809211
Ravi Nair, S. Hong, Sandy Liles, Ray Villani
{"title":"Global Wiring on a Wire Routing Machine","authors":"Ravi Nair, S. Hong, Sandy Liles, Ray Villani","doi":"10.5555/800263.809211","DOIUrl":"https://doi.org/10.5555/800263.809211","url":null,"abstract":"A new global wiring algorithm designed for implementation on special purpose physical design machines is described. This algorithm computes more accurate estimates of wiring channel demand and supply than other known algorithms. It also makes better use of this information in determining wire routes. By exploiting the parallel processing capability of an interconnected array of microcomputers, the global wiring is completed effectively and quickly even for large chips.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116975107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 44
A "Non-Restrictive" Artwork Verification Program for Printed Circuit Boards 印刷电路板的“非限制性”图稿验证程序
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809258
David Kaplan
{"title":"A \"Non-Restrictive\" Artwork Verification Program for Printed Circuit Boards","authors":"David Kaplan","doi":"10.1145/800263.809258","DOIUrl":"https://doi.org/10.1145/800263.809258","url":null,"abstract":"This paper describes a PCB artwork verification program which imposes virtually no restrictions on the layout designer. The program is capable of making fast and reliable verifications of layouts of any type and style. The concepts and techniques used to achieve the \"non-restrictive\" feature of the program are discussed. A unique characteristic of the program is the special treatment of non-electrical elements. The program has been proven by continuous practical use in a dynamic production environment.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127454647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transmission Gate Modeling in an Existing Three-Value Simulator 现有三值模拟器中的传输门建模
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809275
R. M. McDermott
{"title":"Transmission Gate Modeling in an Existing Three-Value Simulator","authors":"R. M. McDermott","doi":"10.1145/800263.809275","DOIUrl":"https://doi.org/10.1145/800263.809275","url":null,"abstract":"Existing three value (0, 1, X,) logic simulators cannot support the use of MOS transmission gates, but this deficiency can be easily eliminated by the addition of one logic value - the high impedance (Z) state. This paper demonstrates that complete transmission gate modeling, including bi-directional operation and Ratio Logic, can be accomplished with this single Z state and explicit node models; and, since four states require the same internal storage as three states, such an enhancement would not require a major software rewrite.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126111146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Testing Functional Faults in VLSI VLSI中的功能故障测试
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809234
Y. Min, S. Su
{"title":"Testing Functional Faults in VLSI","authors":"Y. Min, S. Su","doi":"10.1145/800263.809234","DOIUrl":"https://doi.org/10.1145/800263.809234","url":null,"abstract":"Functional testing has become increasingly important due to the advent of VLSI technology. This paper presents a systematic procedure for generating tests for detecting functional faults in digital systems described by the register transfer language. Procedures for testing register decoding, instruction decoding, data transfer, data storage and data manipulation function faults in microprocessors are described step-by-step. Examples are given to illustrate the procedures.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124978592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Modular Description/Simulation/Synthesis using DDL 使用DDL的模块化描述/仿真/综合
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809224
S. Shiva, J. Covington
{"title":"Modular Description/Simulation/Synthesis using DDL","authors":"S. Shiva, J. Covington","doi":"10.1145/800263.809224","DOIUrl":"https://doi.org/10.1145/800263.809224","url":null,"abstract":"With the increased complexity of integrated circuits, a true top-down methodology is mandatory in their design. A construct that enables a modular description of a system design is added to DDL. The Translator, Simulator and Synthesis Software has been modified to retain this modularity throughout the design cycle. These enhancements allow a multi-level simulation and multi-technology synthesis of an integrated circuit.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131584771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An Efficient Variable-Cost Maze Router 一种高效的可变成本迷宫路由器
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809240
Robert K. Korn
{"title":"An Efficient Variable-Cost Maze Router","authors":"Robert K. Korn","doi":"10.1145/800263.809240","DOIUrl":"https://doi.org/10.1145/800263.809240","url":null,"abstract":"A variable cost maze router is described. The router is substantially faster than most other maze routers and also provides a flexibility which is valuable in a variety of ways. It is particularly well suited for use on multiple layer routing surfaces in which adjacent layers have primary wire directions which are perpendicular to each other. The router has been incorporated as a final phase into both a circuit board routing system and an LSI gate array router. Experience with these systems is described. Potential applications of the variable cost ability are also discussed.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126499065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
The EXCELL Method for Efficient Geometric Access to Data 高效几何访问数据的excel方法
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809228
Markku Tamminen, R. Sulonen
{"title":"The EXCELL Method for Efficient Geometric Access to Data","authors":"Markku Tamminen, R. Sulonen","doi":"10.1145/800263.809228","DOIUrl":"https://doi.org/10.1145/800263.809228","url":null,"abstract":"The extendible cell (EXCELL) method provides a data structure for efficient geometric access. It stores geometric data into computer storage blocksm corresponding to disjoint variable sized rectangular cells accessible by an address calculation type directory. We describe the method for point files and files of more complicated figures analyzing performance. We report algorithms for the nearest neighbour and point-in-polygon-network problems and describe applications to geographical data bases, hidden line elimination and geometric modeling.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133226565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 90
A Utilitarian Approach to CAD 实用的CAD方法
19th Design Automation Conference Pub Date : 1900-01-01 DOI: 10.1145/800263.809181
T. Thompson
{"title":"A Utilitarian Approach to CAD","authors":"T. Thompson","doi":"10.1145/800263.809181","DOIUrl":"https://doi.org/10.1145/800263.809181","url":null,"abstract":"The benefits of using and writing software utilities are appreciated by most software engineers. However, many Computer-Aided Design (CAD) systems do not take full advantage of this technology. This could be because good utilities do not exist, because CAD developers are not aware of existing utilities, or because developers do not know what features to include and leave out when they are writing their own utilities. As with much of computer science, the art of effectively using and writing software utilities has remained just that: an art. This paper discusses the desirable features of good software utilities for CAD and describes techniques that encourage effective use of existing utilities as well as the specification and implementation of new ones. Throughout the paper, experiences from a four year development effort in Designer's Workbench (DWB) [1] are used as examples (both good and bad).","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134357965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信