{"title":"A Database Management System for Design Engineers","authors":"Jack Bennett","doi":"10.1145/800263.809217","DOIUrl":"https://doi.org/10.1145/800263.809217","url":null,"abstract":"This paper describes datamanager and database facilities designed to support a computer-aided electronic design system. Datamanager facilities are those for managing files without regard to their contents; database facilities are those for managing the contents of files. Taken together, these facilities provide transparent and user-controlled services for managing the considerable amounts of information which can be generated in CAD environments.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133013847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Routing Two-Point Nets Across a Channel","authors":"R. Pinter","doi":"10.1145/800263.809305","DOIUrl":"https://doi.org/10.1145/800263.809305","url":null,"abstract":"Many problems that arise in general channel routing manifest themselves in simpler situations. We consider connecting a set of n terminals on a line to another set on a parallel line across a rectangular channel. We show that in any solution to the problem that (almost) minimizes the width of the channel (i.e. the distance between the lines the terminals reside on), (i) a net may require as many as O(vn) jogs, (ii) no net routed from top to bottom need ever turn upward in the middle. We also present an efficient algorithm to obtain minimal jogging in river routing, and provide necessary and sufficient conditions for conflict cycle resolution. These and other results are presented in the context of a general survey on routing from a combinatorial complexity point of view.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114922039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Designing Gate Arrays Using a Silicon Compiler","authors":"J. P. Gray, I. Buchanan, P. S. Robertson","doi":"10.1145/800263.809233","DOIUrl":"https://doi.org/10.1145/800263.809233","url":null,"abstract":"This paper describes a programming environment in which gate array designs can be developed. It allows the engineer to design for performance, wirability and testability by manipulating a textual description of a design. The principle features of this are a high-level language for design description, completely automatic layout, and an integrated simulator. The total package can be referred to as a silicon compiler in the gate array design style.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114672927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Verification Testing","authors":"E. McCluskey","doi":"10.1145/800263.809250","DOIUrl":"https://doi.org/10.1145/800263.809250","url":null,"abstract":"A new approach to test pattern generation which is particularly suitable for self-test is described. Required computation time is much less than for present-day automatic test pattern generation (ATPG) programs. Fault simulation is not required. More patterns may be obtained than from standard ATPG programs. However, fault coverage is much higher - all irredundant multiple as well as single stuck faults are detected. Test length is easily controlled. The test patterns are easily generated algorithmically either by program or hardware.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134088667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hierarchical Top-Down Layout Design Method for VLSI Chip","authors":"T. Adachi, H. Kitazawa, M. Nagatani, T. Sudo","doi":"10.1145/800263.809291","DOIUrl":"https://doi.org/10.1145/800263.809291","url":null,"abstract":"A new hierarchical top-down layout design system for custom VLSIs has been developed. A top-down global route assignment process reduces the redundant wiring area. Routing in a single path over the whole chip enables efficient chip area use.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121821070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Experiments Using Interactive Color Raster Graphics for CAD","authors":"Abe R. Shliferstein","doi":"10.1145/800263.809243","DOIUrl":"https://doi.org/10.1145/800263.809243","url":null,"abstract":"Color raster graphics is being incorporated into CAD systems for printed circuit board (PCB) design. An interactive prototype CAD system developed as an experimental base is described, along with color graphics research using this prototype. Areas investigated included the generation and display of complex PCB's, the display of depth information using \"2 1/2 dimensional\" techniques, performance measurements on color raster systems, possibilities for new on-line design audit techniques, color graphics primitives, hardware and software architectures, and human factors considerations.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121807893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"SAGA: An Experimental Silicon Assembler","authors":"A. Szepieniec","doi":"10.1145/800263.809231","DOIUrl":"https://doi.org/10.1145/800263.809231","url":null,"abstract":"The paper presents an IC-layout assembler which is capable of transforming the structural description of a system into general chip layout expressed in CIF. The chip assembly is based on the efferent decision flow. The process is one of gradual refinement of the starting domain yielding successively lower level chip components down to the primitives.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125161083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Lyra: A New Approach to Geometric Layout Rule Checking","authors":"Michael H. Arnold, J. Ousterhout","doi":"10.1145/800263.809255","DOIUrl":"https://doi.org/10.1145/800263.809255","url":null,"abstract":"Lyra is a layout rule checking program for Manhattan VLSI circuits. In Lyra, rules are specified in terms of constraints that must hold at certain corners in the design. The corner-based mechanism permits a wide variety of rules to be specified easily, including rules involving asymmetric constructs such as transistor overhangs. Lyra's mechanism also has locality, which can be exploited to construct incremental and/or hierarchical checkers. A rule compiler translates symbolic rules into efficient code for checking those rules, and permits the system to be retargeted for different processes.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125544717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Layout System for High Precision Design of Progressive Die","authors":"Kazuyuki Inoue, M. Adachi, T. Funayama","doi":"10.1145/800263.809214","DOIUrl":"https://doi.org/10.1145/800263.809214","url":null,"abstract":"This paper describes new algorithms for designing die layout and die components to be constructed by punch and die. A software system for implementing the algorithms in an integrated CAD design process is also described.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128877844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Fault Simulation Methodology for VLSI","authors":"J. Hayes","doi":"10.1145/800263.809235","DOIUrl":"https://doi.org/10.1145/800263.809235","url":null,"abstract":"Some deficiencies of existing simulators in the context of VLSI design and testing are considered. A fault simulation approach based on CSA (connector-switch-attenuator) theory is defined which overcomes many of these deficiencies. The CSA circuit elements and logic values needed to model combinational circuits are described and applied to the analysis of various types of MOS circuits. A charge-storage element called a well is introduced to simulate sequential behavior. It is shown that many fault types, including stuck-line faults, short circuits, open circuits, and delay faults can be modeled in a uniform and efficient manner.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126447169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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