{"title":"A \"Greedy\" Channel Router","authors":"Ronald L. Rivest, C. M. Fiduccia","doi":"10.1145/62882.62912","DOIUrl":"https://doi.org/10.1145/62882.62912","url":null,"abstract":"We present a new, \"greedy\", channel-router that is quick, simple, and highly effective. It always succeeds, usually using no more than one track more than required by channel density. (It may be forced in rare cases to make a few connections \"off the end\" of the channel, in order to succeed.) It assumes that all pins and wiring lie on a common grid, and that vertical wires are on one layer, horizontal on another. The greedy router wires up the channel in a left-to-right, column-by-column manner, wiring each column completely before starting the next. Within each column the router tries to maximize the utility of the wiring produced, using simple, \"greedy\" heuristics. It may place a net on more than one track for a few columns, and \"collapse\" the net to a single track later on, using a vertical jog. It may also use a jog to move a net to a track closer to its pin in some future column. The router may occasionally add a new track to the channel, to avoid \"getting stuck\".","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122207569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling Polyhedral Solids Bounded by Multi-Curved Parametric Surfaces","authors":"Y. Kalay","doi":"10.1145/800263.809251","DOIUrl":"https://doi.org/10.1145/800263.809251","url":null,"abstract":"Since the beginning of geometric modeling as a field of CAD a decade ago, the methods for interactive design of solid objects and interactive design of free-formed surfaces (of degree 3 and higher) were developed along parallel but disjoint strands. One led to the development of techniques for representing and manipulating the shape of polyhedral solids bounded mostly by planes, while the other led to the development of techniques for the mathematical representation of curved surfaces, without paying attention to their combination into volumetric solids. Though the need for integrating solid object modeling with surface modeling for the design of such artifacts as machine parts, aircraft, cars and ships has been widely recognized, there is so-far no modeling system which provides such capabilities in a general way. An integrated solids modeling system for representing and manipulating polyhedral objects bounded by bicubic parametric surfaces, is presented. Its basic capabilities include the representation of solids through a surface-based model, such that the surface underlying any face can be replaced by another surface that has been modeled independently. Other functionalities include scaling, rotation and translation of shapes, and their pairwise combination into more complex shapes by means of spatial set operators.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133049990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Interactive Symbolic Design for VLSI Modules","authors":"R. Larsen, J. A. Luisi, Ashutosh Kumar Singh","doi":"10.1109/DAC.1982.1585514","DOIUrl":"https://doi.org/10.1109/DAC.1982.1585514","url":null,"abstract":"The representation of circuit topology, using symbols, was pioneered by Rockwell International in the mid 1960s. This methodology is now recognized as a significant means for managing the growing complexity of VLSI design. A generalization of this symbolic design methodology has been under development at Rockwell International since 1979. The objective is the realization of an affordable design station, in the engineer's office, to create an informal design environment that promotes innovative composition with analysis of circuit performance. The computer-aided design methodology is highly interactive, very simple, and utilizes color-enhanced symbolic graphic constructs called ALPs. The ALPs are sets of grid points, Areas, Lines and Points, committed to represent the physical structures such as conductors, contacts and FETs. A color graphics display enables bilateral, pictorial communications between designer and computer. Interactive features of the methodology include concurrent design rule checking, node labeling, and the resolution of design intentions as the designer is interactively composing symbolic circuit topology. A mask geometries algorithm transforms the symbolic representation of circuit topology into the precise mask set required by any silicon foundry or fabricator. Each process is characterized to the mask geometries algorithm as a three-dimensional matrix. The matrix-elements define geometric attributes called SIZE, COVER and PROTECT which characterize the present state of a particular process-plant. An interactive editor provides a convenient means for altering geometrical data to the mask geometries algorithm. The algorithm generates mask polygonal outlines, displayed in color for any selected viewing window. A tracking ruler allows the designer to easily perform inter and intra-mask feature measurements. Limited testing in a research environment indicates that significant gains are achievable in designer productivity while encouraging engineering excellence with regard to VLSI device performance and density.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121748339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of Command for CAD Systems","authors":"L. A. Price","doi":"10.1145/800263.809244","DOIUrl":"https://doi.org/10.1145/800263.809244","url":null,"abstract":"Dynamic, hierarchical, command menus are practical when 1) certain entered commands can be used to predict the following commands (in other words, when there exist commands that stimulate a change of menu) and 2) when a small, changing menu is preferable to a large menu that includes the entire command set. A project on possible menu form tested the relevance of the first of these criteria to a friendly graphics environment. The order in which commands were entered during production use of an IC design system was analyzed. Results not only indicate that the criterion is met, but also suggest the form of a possible dynamic menu.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121729676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Z. Gingerich, M. P. Carroll, E. J. Chelius, Po-Kuan Lu
{"title":"A Hybrid CAD/CAM System for Mechanical Applications","authors":"J. Z. Gingerich, M. P. Carroll, E. J. Chelius, Po-Kuan Lu","doi":"10.1145/800263.809270","DOIUrl":"https://doi.org/10.1145/800263.809270","url":null,"abstract":"The current wire frame and surface modeling based CAD/CAM systems provide productive tools for the mechanical manufacturing industries. Volumetric modeling, distributed processing, 3-dimensional graphic displays, relational data bases, and less expensive, more powerful computers are emerging technologies sure to benefit CAD/CAM applications. The challenge of the 80's is to integrate the proven CAD/CAM techniques of the 70's with these emerging technologies. This paper addresses the issues involved in the integration by presenting the concepts of a Hybrid CAD/CAM system designed for the 80's.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115017051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Richard L. Donze, J. Sanders, M. Jenkins, G. Sporzynski
{"title":"PHILO - A VLSI Design System","authors":"Richard L. Donze, J. Sanders, M. Jenkins, G. Sporzynski","doi":"10.1145/800263.809202","DOIUrl":"https://doi.org/10.1145/800263.809202","url":null,"abstract":"This paper describes a design system capable of designing chips in the range of 5K to 7K equivalent three-way NOR gates. A key feature of the system is the ability to design chips with large macros (RAMs and PLAs). This design system is part of IBM's corporate-wide Engineering Design System (EDS). EDS provides the capabilities of logic simulation, automatic placement and wiring, checking, and test pattern generation [1]. This paper describes the key capabilities of the system, specifically as applied to IBM's silicon gate process. Topics covered include a description of the chip image and circuits, the automatic generation of large macros, the automatic placement and interconnection of circuits and macros, and a delay calculator/optimizer.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115002716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Toward VLSI Complexity : The DA Algorithm Scaling Problem : Can Special DA Hardware Help?","authors":"H. Adshead","doi":"10.1145/800263.809227","DOIUrl":"https://doi.org/10.1145/800263.809227","url":null,"abstract":"With the increasing scale of integration we need to employ DA algorithms to assist us in managing the complexities involved. Many of our current techniques are already costly and slow and yet scale by some power law as the gate count increases. An analysis of the strategies open to us leads to the possibility that in many cases specialised DA hardware is cost effective. This paper then describes a series of trials to employ a 64 x 64 distributed array processor at DA tasks. Some unexpected results were obtained as algorithms evolved in the area of tracking, simulation, placement, test generation, fault simulation, and layout rule checking. The paper concludes with a discussion of the overheads incurred in employing unconventional hardware.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Symbolic Design System for Integrated Circuits","authors":"K. Keller, A. Newton, S. Ellis","doi":"10.1145/800263.809245","DOIUrl":"https://doi.org/10.1145/800263.809245","url":null,"abstract":"As integrated circuit design has become increasingly complex, the need for more effective data description techniques has become critical. Design verification from mask artwork data alone can consume vaste amounts of computer time for VLSI circuits, if it can be performed at all. The use of a symbolic design description, which allows the designer or synthesis program to express circuit structure as well as maintain full connectivity information, can reduce dramatically the burden placed on the verification tools. This paper describes a symbolic design system, its associated data manager, its color graphics viewport manager, and its application to a variety of design methods. The data manager can store a variety of representations of the design, including simulation data, geometric layout, symbolic layout, and schematic diagrams. The viewport manager can manage a number of viewports concurrently and the use of a model frame buffer allows it to function easily on a variety of graphics terminals and hard-copy devices. The system is designed with an engineering work station in mind.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121013082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evolution of the Engineering Design System Data Base","authors":"Jere L. Sanborn","doi":"10.1145/800263.809209","DOIUrl":"https://doi.org/10.1145/800263.809209","url":null,"abstract":"The IBM Engineering Design System is a corporate-wide electronic design automation system used for the development of the 3081 and other machines incorporating LSI chips and their carriers. Initially planned in the late 1960s, the system has evolved to respond to a changing set of requirements. This paper describes the evolution of the system data base, as well as the steps taken to ensure the integrity of the data and the correctness of the design.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122731360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hardware Description Language for Processor Based Digital Systems","authors":"J. H. Tracey, Kovvali Surya Kumar","doi":"10.1145/800263.809225","DOIUrl":"https://doi.org/10.1145/800263.809225","url":null,"abstract":"A new HDL (Hardware Description Language) for describing processor modules and support chips is presented in [1][2]. This paper presents a portion of the dissertation and illustrates the effectiveness of the new descriptive technique in describing complex digital systems with example descriptions of the PDP-11 computer system and the 2900 bit-slice components. The examples presented illustrate that the descriptive technique allows functional abstraction not only at the chip interface level (as in the M6800 system description presented in [1][2]) but also at the subsystem (or PCB module) level (as shown in the PDP-11 example). Language modifications and enhancements to increase the power of the language are also presented.","PeriodicalId":290739,"journal":{"name":"19th Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124580310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
