PHILO - A VLSI Design System

Abstract

This paper describes a design system capable of designing chips in the range of 5K to 7K equivalent three-way NOR gates. A key feature of the system is the ability to design chips with large macros (RAMs and PLAs). This design system is part of IBM's corporate-wide Engineering Design System (EDS). EDS provides the capabilities of logic simulation, automatic placement and wiring, checking, and test pattern generation [1]. This paper describes the key capabilities of the system, specifically as applied to IBM's silicon gate process. Topics covered include a description of the chip image and circuits, the automatic generation of large macros, the automatic placement and interconnection of circuits and macros, and a delay calculator/optimizer.