Interactive Symbolic Design for VLSI Modules

Abstract

The representation of circuit topology, using symbols, was pioneered by Rockwell International in the mid 1960s. This methodology is now recognized as a significant means for managing the growing complexity of VLSI design. A generalization of this symbolic design methodology has been under development at Rockwell International since 1979. The objective is the realization of an affordable design station, in the engineer's office, to create an informal design environment that promotes innovative composition with analysis of circuit performance. The computer-aided design methodology is highly interactive, very simple, and utilizes color-enhanced symbolic graphic constructs called ALPs. The ALPs are sets of grid points, Areas, Lines and Points, committed to represent the physical structures such as conductors, contacts and FETs. A color graphics display enables bilateral, pictorial communications between designer and computer. Interactive features of the methodology include concurrent design rule checking, node labeling, and the resolution of design intentions as the designer is interactively composing symbolic circuit topology. A mask geometries algorithm transforms the symbolic representation of circuit topology into the precise mask set required by any silicon foundry or fabricator. Each process is characterized to the mask geometries algorithm as a three-dimensional matrix. The matrix-elements define geometric attributes called SIZE, COVER and PROTECT which characterize the present state of a particular process-plant. An interactive editor provides a convenient means for altering geometrical data to the mask geometries algorithm. The algorithm generates mask polygonal outlines, displayed in color for any selected viewing window. A tracking ruler allows the designer to easily perform inter and intra-mask feature measurements. Limited testing in a research environment indicates that significant gains are achievable in designer productivity while encouraging engineering excellence with regard to VLSI device performance and density.